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Questa One (34)
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IEEE 1801 (33)
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DO-254 (31)
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Modeling (30)
TLM (30)
osmosis 2022 (30)
Accellera (29)
CDC Methodology (29)
Power Domain (29)
Properties (29)
Register Model (29)
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UVM Debug (28)
ASIC (27)
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Classes (27)
Introduction to UVM (27)
Lint (27)
Patterns (27)
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Functional Simulation (26)
Metastability (26)
PCIe (26)
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Verilog (26)
Waveform (26)
Archive (25)
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Block Level (24)
Design Trends (24)
Driver (24)
Fault Campaign (24)
Formal Analysis (24)
Object Oriented Programming (24)
UVM Basics (24)
Co-Emulation (23)
Cookbook (23)
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Testplan (23)
osmosis 2024 (23)
Assurance (22)
Data-driven Verification (22)
Lifecycle (22)
Non-Trivial Bug Escapes (22)
Big Data (21)
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Constrained Random Verification (21)
Coverage Metrics (21)
Covergroup (21)
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Performance (21)
U2U (21)
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Acceleration (20)
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C (20)
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Design Constructs (20)
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Hardware Fault (20)
VRM (20)
X-Tracing (20)
Abstraction (19)
Config_db (19)
Interactive Mode (19)
Netlist (19)
Packages (19)
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Python (19)
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API (18)
Asynchronous Clock (18)
Automation (18)
Code Generator (18)
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Data Types (18)
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Sequence Item (18)
Sequencer (18)
System Level (18)
Verification Practice (18)
Advanced Debug Techniques (17)
Design for Test (17)
Electronic Systems (17)
Fault Injection (17)
Livesim (17)
Object-Oriented Programming in SystemVerilog (17)
Power States (17)
Scenario Generation (17)
Sequence Driver (17)
State Space (17)
Testbench Automation (17)
U2U Europe (17)
Verification Run Manager (17)
Virtual Sequences (17)
Arrays (16)
BFMs (16)
Configuration Database (16)
Continuous Integration (16)
Gate-Level (16)
Interoperability (16)
Signal (16)
CDC Analysis (15)
Inconclusives (15)
Intelligent Automation (15)
QVIP Configurator (15)
Reset-Domain Checking (15)
Universal Chiplet Interconnect Express (15)
Variable (15)
ABV (14)
Assertion-Based Verification (14)
Automotive Functional Safety Forum (14)
COCOTB (14)
Chiplets (14)
Customization (14)
Expressions (14)
Failure Analysis (14)
Fault Simulation (14)
Glitches (14)
HLS (14)
Jenkins (14)
Macros (14)
March 2016 - Volume 12 Issue 1 (14)
Monitors (14)
Productivity Gap (14)
Register Layer Adapter (14)
SLEC (14)
Stimulus Generation (14)
UCIe (14)
UVMC Kit (14)
Verification Closure (14)
AXI (13)
Continuous Integration System (13)
DFT Verification (13)
Design Complexity (13)
FPGA Prototyping (13)
Formal Application (13)
Gate-Level Simulation (13)
Power Intent (13)
Python for Verification Series (13)
Sub-system (13)
X-Propagation (13)
ASIL (12)
Adoption Trends (12)
Agent (12)
Coverage Models (12)
DVCon Japan (12)
Data Mining (12)
Data Models (12)
Declaration (12)
Environment Pattern (12)
Hardware Acceleration (12)
Hierarchical Components (12)
Interrupts (12)
Multi-Die (12)
NVMe (12)
Parameterized Classes (12)
September 2021 - Volume 17 Issue 2 (12)
Unit Testing (12)
Verification IQ (12)
Aerospace and Defense Verification Tech Day (11)
Analog (11)
Connections (11)
Creating and Using Constrained Random (11)
DPI-C (11)
Generation (11)
Interview (11)
June 2015 - Volume 11 Issue 2 (11)
June 2017 - Volume 13 Issue 2 (11)
Memory Models (11)
Methods (11)
Mixed-Signal Verification (11)
OVM (11)
Operators (11)
PYUVM (11)
Processor Design Verification (11)
RDC Design (11)
Reachability Checks (11)
Register Package (11)
Test Environment (11)
Tool Assessment (11)
VIQ (11)
Verification Process Overview (11)
AMBA (10)
Backdoor Accesses (10)
Checkers (10)
Class Handles (10)
Class Reference (10)
Co-Simulation (10)
Command API (10)
Deadlock (10)
Fault Analysis (10)
Fault Grading (10)
High Speed (10)
IC Reliability (10)
Inheritance (10)
Interconnect (10)
July 2022 - Volume 18 Issue 2 (10)
June 2013 - Volume 9 Issue 2 (10)
Matlab (10)
Model Checking (10)
Parallel Simulation (10)
Predictive Analysis (10)
Proof Coverage (10)
Property Debug (10)
Report (10)
Reset Architecture (10)
Root of Trust (10)
Safety Metrics (10)
Timing (10)
Traceability (10)
Unified Power Format (10)
Verification Component (10)
osmosis 2025 (10)
3DIC (9)
Bitstream (9)
Breakpoint (9)
CDC Path (9)
CDC Protocol (9)
Class Objects (9)
Configuration Object (9)
Creating and Using Functional Coverage (9)
Curriculum (9)
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Data Types and Procedural Statements (9)
Encapsulation (9)
Formal Assertion-Based Verification (9)
Hierarchical Sequences (9)
Iterations (9)
June 2012 - Volume 8 Issue 2 (9)
June 2014 - Volume 10 Issue 2 (9)
June 2018 - Volume 14 Issue 2 (9)
Learning Paths (9)
Monitor (9)
Multi-Core Architectures (9)
Parameter (9)
Randomization (9)
Reference Model (9)
Retention (9)
SPI (9)
Sequence-Driver Use Models (9)
Siemens Xcelerator Academy (9)
Skill Building (9)
Training (9)
UVM Stimulus, Tests, and Regressions (9)
VHDL-2008 (9)
Whats New in Functional Verification (9)
1800.2 (8)
Algorithms (8)
B/C/R Script (8)
Clock Gating (8)
Convergence (8)
Coverage Goals (8)
Cross Coverage (8)
DMA Engine (8)
Design and Verification IP Forum (8)
Directed Test (8)
Ethernet (8)
Factory Pattern (8)
February 2013 - Volume 9 Issue 1 (8)
HDL Domain (8)
HTML Docs (8)
Hardware Security (8)
Isolation (8)
June 2016 - Volume 12 Issue 2 (8)
March 2021 - Volume 17 Issue 1 (8)
Messaging (8)
Metrics-Driven (8)
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OSCI (8)
OVM2UVM (8)
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Release (8)
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State Machine (8)
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Supply Set (8)
UALink (8)
UCIe 2.0 (8)
UVM Verification (8)
Verification Architecture (8)
osmosis 2023 A&D (8)
ADAS (7)
AI Algorithms (7)
Bind (7)
Cache Coherency (7)
Clocking Verification Challenges (7)
Conditionals (7)
Connecting the Testbench to the Design (7)
Conversion (7)
DAC 2019 (7)
Design Assurance (7)
Design IP (7)
Design Integrity (7)
Diagnostic Coverage (7)
Error Injection (7)
Error Traces (7)
Execution Semantics and Synchronization (7)
HPC (7)
High-Level Synthesis (7)
IP Blocks (7)
IP Security (7)
ISA (7)
Implementation Model (7)
Israel Static & Formal Tech Day (7)
July 2020 - Volume 16 Issue 2 (7)
LLMs (7)
Layering (7)
March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Metastable (7)
Migration (7)
Modules (7)
November 2014 - Volume 10 Issue 3 (7)
November 2015 - Volume 11 Issue 3 (7)
Order Property Pattern (7)
Parameterized Tests (7)
Pin Level (7)
Postsim (7)
Power Analysis (7)
Power Estimation (7)
Power Logic (7)
Power Optimization (7)
Predictors (7)
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RDC Violations (7)
Reconvergence (7)
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Schematic (7)
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Siemens EDA (7)
Specification (7)
Static Checks (7)
Strategy (7)
Structural Analysis (7)
System Scaling (7)
TLM FIFOS (7)
Technology Scaling (7)
Test Generation (7)
Test Verification (7)
Testbench Architecture (7)
Testbench Customization in UVM (7)
Testing Strategies (7)
Tool Qualification (7)
Transaction Recording (7)
UCDB (7)
VA Live 2023 - Huntsville (7)
Waivers (7)
X-Checking (7)
X-Corruption (7)
osmosis Europe 2025 (7)
AEH (6)
Address Mapping (6)
Appendix (6)
Artificial Neural Network (6)
Behavioral Modeling (6)
Coverage Intent (6)
Creating and Using a Test Plan (6)
DDR (6)
Data Transfer (6)
December 2017 - Volume 13 Issue 3 (6)
December 2022 - Volume 18 Issue 3 (6)
Design Mitigation (6)
Design Patterns (6)
Digital Design (6)
Distributed Resource Management (6)
Electronic Hardware (6)
Fabric (6)
Front and Back Door (6)
HDM (6)
Hierarchical Flow (6)
High-Speed (6)
IP Integration (6)
June 2019 - Volume 15 Issue 2 (6)
MARLUG 2023 (6)
MBIST (6)
MIPI (6)
March 2014 - Volume 10 Issue 1 (6)
March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
Metric Validation (6)
November 2016 - Volume 12 Issue 3 (6)
November 2020 - Volume 16 Issue 3 (6)
October 2012 - Volume 8 Issue 3 (6)
October 2013 - Volume 9 Issue 3 (6)
Open Source (6)
PSL (6)
Phasing (6)
Power Efficiency (6)
Pre-Silicon (6)
RDC Methodology (6)
Random Faults (6)
Secure Data Path (6)
Slave (6)
UVM Forum (6)
VA Live 2024 - El Segundo (6)
VA Live 2024 - San Diego (6)
VA Live 2025 - El Segundo (6)
VA Live 2025 - Hudson (6)
VA Live 2025 - Huntsville (6)
Validation (6)
Verbosity (6)
Verification Effectiveness (6)
Voltage Domain Crossing (6)
Windows (6)
X-Effects (6)
YAML (6)
osmosis 2024 A&D (6)
ATPG (5)
Advance Your Verification Methodology (5)
Analysis Pattern (5)
BIST (5)
Base Class (5)
Bus Functional Models (5)
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Class Library (5)
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DAC 2018 (5)
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DSP (5)
December 2019 - Volume 15 Issue 3 (5)
Defect Coverage (5)
Design Scaling (5)
Dual Domains (5)
Error (5)
FMEDA (5)
February 2019 - Volume 15 Issue 1 (5)
Flip-Flop (5)
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Formal Testbench (5)
Functional Correctness (5)
Guidelines (5)
HBM4 (5)
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In-Circuit Emulation (5)
JEDEC (5)
Low Power Verification Forum (5)
MARLUG 2024 (5)
March 2018 - Volume 14 Issue 1 (5)
Non-Determinism (5)
Objections (5)
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Quirky (5)
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SVUnit (5)
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Simulink (5)
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Sub-system Level (5)
Test Class (5)
Threads (5)
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Transaction-Level (5)
UCIe 3.0 (5)
Utilization (5)
VA Live 2019 - Westford (5)
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XML (5)
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CHERI (4)
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Data Link (4)
Deprecated (4)
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DisplayPort (4)
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ECO (4)
ED-80 (4)
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ICE Mode (4)
IEEE (4)
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Non-Pipelined (4)
November 2018 - Volume 14 Issue 3 (4)
PCIe Gen 6 (4)
Phases (4)
Plusargs (4)
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QoR (4)
Race Conditions (4)
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Reset Tree (4)
Respins (4)
SVTB (4)
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Test Ranking (4)
Time Cone (4)
UART (4)
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USB (4)
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VA Live 2023 - Austin (4)
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Verification Success (4)
X-Aware (4)
$display (3)
1.2 (3)
AHB (3)
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Certification (3)
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Clocking (3)
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Coroutines (3)
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Cryptography (3)
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Development Environment (3)
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FPU (3)
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Golden Model (3)
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July 2023 - Volume 19 Issue 2 (3)
Jump Statements (3)
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Stream (3)
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TBX (3)
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Transfer Protocols (3)
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Type Casting (3)
UVM 1.1d (3)
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