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1772 Results

  • UVM Connectivity Debug

  • UVM Phase Debug

    In this session we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.

  • UVM Phase Debug

  • Memory Leak Debug

  • Memory Leak Debug

    In this session we will describe what a memory leak is in a UVM environment and how to effectively debug the issue.

  • UVM Configuration Database Debug

  • UVM Configuration Database Debug

    In this session we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.

  • Enterprise Ethernet PHY Verification

    In this session, you will learn about the wide breadth of Ethernet speeds and standards specification supported by Questa Verification IP. You will also learn about the various use models and features available in Questa VIP for verifying an Enterprise Ethernet PHY supporting the latest greatest Ethernet speeds.

  • Need for Speed - PCIe® GEN4 Verification

    In this session, you will be introduced to PCI Express and the latest specification updates in PCI Express Base Specification Revision 4.0.

  • Creating a Thorough Verification Environment in Less Than Two Days

    In this session you will learn how to become more productive by utilizing testbench automation, testbench generation, the UVM Framework and the VIP Configurator.

  • Trends and Requirements in High Speed Interface Verification

    In this session, you will learn about trends and requirements in high speed interface (HSI) verification.

  • MIPI® CSI-2 TX Verification

    This session focuses on the technical details on how the verification of MIPI® CSI-2 Transmitter IP was executed using Questa Verification IPs (CSI-2 and AHB).

  • Leveraging the latest DDR & Flash Memory Models

    In this session, you will learn how to leverage the latest DDR and flash memory models.

  • USB 3.1 Verification Challenges

    In this session, you will learn how to improve USB 3.1 IP quality with functional verification using SystemVerilog.

  • Conquering the New IP Economy

    In this session, Harry Foster will present current industry trends and in both design and verification, and then introduce emerging solutions required to close the verification productivity gap.

  • SoC Verification with the Questa Flow

    In this session, you will learn industry best practices in verification flows and how to implement the optimal flow to speed your SoC design verification cycle.

  • Hardware Emulation: Three Decades of Evolution

  • Sometimes the Life of a College Student and a Verification Engineer Aren’t All That Different

  • Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

    Since UPF was first announced in 2007 by Accellera, many of the early features- like explicit supply port, supply net and the power state table (PST)- governed UPF based low power design verification methodologies mainly from post synthesis levels and onward. However, the recent update of IEEE 1801 3 specifies intrinsic flexibility to associate a power domain with a supply set and implicate infinite ordered list of power states, augmented with incrementally refinable arguments for the objects.

  • Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

    The recent edition of IEEE 1801 specifies the power state table (PST) construct should be phased out as legacy, and instead be replaced by the new semantics of the 'add_power_state' UPF command. This paper starts with investigating the limitations of legacy PST in a complex SoC design verification environment, and how to reap the benefits of the incrementally refinable power state features through the fundamental constructs of 'add_power_state'.

  • Testbench Automation - Environment

    In this session, you will learn how to use the UVM-Framework code generation to rapidly build reusable testbench infrastructure.

  • Testbench Automation - Introduction

    In this session, you will learn how to create a complex testbench that can be targeted at simulation or emulation in a couple of hours.

  • Testbench Automation - Testbench

    In this session, you will learn how Portable Stimulus shortens the time to create efficient, systematic scenario-level stimulus.

  • Testbench Automation - Interfaces

    In this session, you will learn how to use a VIP Configurator to shorten the bring up time for industry standard protocols.

  • Use Formal to Check Logic Faults

    In this session, you will learn how to use Formal to check if your RTL is sensitive to any logic faults, and how can you verify that the internal safety mechanism handles them to avoid a catastrophic failure.