Search Results

Advanced Search

2154 Results

Layered Sequences

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Layered Sequences

Session - May 25, 2021 by Tom Fitzpatrick

This session shows how to create a virtual sequence, which controls the execution of other sequences and how to model layered protocols.
Setting Up the Register Layer

Session - May 25, 2021 by Tom Fitzpatrick

This session introduces the UVM Register Layer, showing you how to create register models that reflect the operation of the hardware registers in your DUT.
Writing and Managing Tests

Session - May 25, 2021 by Tom Fitzpatrick

This session shows how to create a set of tests derived from a base test that defines the default setup of your environment, including how to invoke specific tests from the command line.
Writing and Managing Tests

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Setting Up the Register Layer

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Using the Register Layer

Session - May 25, 2021 by Tom Fitzpatrick

This session discusses the various methods that a test can use to access the register model, including both “front-door” and “back-door” accesses.
Using the Register Layer

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick

Using the Register Layer will also show how to create register-bases stimulus sequences to simplify the API.
Register-Based Testing

Session - May 25, 2021 by Tom Fitzpatrick

This session shows how to round out your register-based test environment with register-level scoreboards and functional coverage.
Register-Based Testing

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Advanced UVM

Track - May 25, 2021 by Tom Fitzpatrick

Advanced UVM builds upon the concepts covered in Basic UVM to take your UVM understanding to the next level.
The Three Witches: Preventing Glitch Nightmares on CDC Paths

Paper - May 18, 2021 by Ping Yeung

As electronic design companies are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals reduce reliability and lead to potential silicon failures. To identify potential glitches at the gate level, Questa Signoff CDC uses structural CDC analysis, expression analysis, and an automated formal-based glitch detection methodology to identify real glitches in a design.
The Three Witches: Preventing Glitch Nightmares on CDC Paths

Resource (Paper (.PDF)) - May 18, 2021 by Ping Yeung

In this paper, we first explain the glitch problems in various types of CDC paths. Then we summarize an automated formal-based glitch detection methodology.
Machine Learning at the Edge: Using HLS to Optimize Power and Performance

Resource (Paper (.PDF)) - May 12, 2021 by Michael Fingeroff - Siemens EDA

Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet next-generation machine learning hardware demands at the edge.
Formal 101: Setting Up & Optimizing Constraints

Session - May 10, 2021 by Mark Eslinger

In this session we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints themselves, your test plan and formal coverage plan, and the DUT behavior.
Setting Up & Optimizing Constraints

Resource (Slides (.PDF)) - May 10, 2021 by
Optimizing a Fault Campaign for Complex Mixed-Signal Devices

Webinar - May 04, 2021 by Jake Wiltgen

In this session, you will learn details how to effectively set up and execute an ISO 26262 fault campaign for mixed signal designs and establishing an efficient fault injection workflow for analog and digital portions of the design.
Low Power Considerations for Verification

Webinar - Apr 29, 2021 by Rick Koster

Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.
Formal 101: Basic Abstraction Techniques

Session - Apr 21, 2021 by Jin Hou

In this session we will teach about the types of DUT constructs that commonly cause trouble for the formal analysis, and how to apply time-tested techniques to safely abstract them away so that the formal verification run can rapidly reach closure.
A Methodology for Comprehensive CDC+RDC Analysis

Resource (Slides (.PDF)) - Apr 20, 2021 by Kurt Takara

In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability.
A Methodology for Comprehensive CDC+RDC Analysis

Webinar - Apr 20, 2021 by Kurt Takara

In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability.
Easy Test Writing with a Proxy-driven Testbench

Webinar - Apr 06, 2021 by Ray Salemi

In this session we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.
Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog

Resource (Paper (.PDF)) - Mar 31, 2021 by
Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog

Resource (Paper (.PDF)) - Mar 31, 2021 by
Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology

Resource (Slides (.PDF)) - Mar 31, 2021 by Michael Fingeroff - Siemens EDA

This workshop will demonstrate how pre-hls simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found till very late in a hand-coded RTL design methodology.