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Simplifying Mixed-Signal Verification
Article - Nov 28, 2018 by
Mixed-signal design is the art of taking real world analog information, such as light, touch, sound, vibration, pressure, or temperature, and bringing it into the digital world for processing.
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Functional Verification Study - 2018
Session - Oct 15, 2018 by Harry Foster
In this session, Harry Foster highlights the key findings from the 2018 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
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DO-254 in Simple Terms
Resource (Slides) - Oct 10, 2018 by Byron Brinson
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Planning for DO-254
Resource (Slides) - Oct 10, 2018 by Byron Brinson
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DO-254 in Simple Terms
Session - Oct 04, 2018 by Byron Brinson
In this session, you will be introduced to DO-254 from a designer’s perspective in layman’s terms and will be gain a fundamental understanding of what DO-254 is and its applications.
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Planning for DO-254
Session - Oct 04, 2018 by Byron Brinson
In this session, we will discuss what is involved in planning phase for DO-254. It is intended to give the view insight on the planning artifacts and their content.
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Introduction to DO-254
Track - Oct 04, 2018 by Byron Brinson
DO-254 has been around for over 15 years and has been applied almost exclusively in the commercial Aerospace industry. Because it has been focused in a subset of the electronic hardware market, many engineers and companies have little to no knowledge of DO-254.
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How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety
Article - Oct 04, 2018 by Verification Horizons
Integrated circuits used in high-reliability applications must demonstrate low failure rates and high levels of fault detection coverage. Safety Integrity Level (SIL) metrics indicated by the general IEC 61508 standard and the derived Automotive Safety Integrity Level (ASIL) specified by the ISO 26262 standard specify specific failure (FIT) rates and fault coverage metrics (e.g., SPFM and LFM) that must met.
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A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products
Article - Oct 04, 2018 by Verification Horizons
Functional safety is a critical concern for all automotive products, and the most complex and least understood part of it is safety from random faults (faults due to unpredictable natural phenomena rather than design bugs). ISO 26262, "Road vehicles — Functional safety" sets out the requirements for safe designs.
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Emulation Based Approach to ISO 26262 Compliant Processors Design
Article - Oct 04, 2018 by Verification Horizons
All types of electronic systems can malfunction due to external factors. The main sources causing faults within electronic components are radiation, electromigration and electromagnetic interference. The evaluation of a fault- tolerant system is a complex task that requires the use of different levels of modeling. Compared with other possible approaches such as proving or analytical modeling, fault injection is particularly attractive.
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AMS Verification for High Reliability and Safety Critical Applications
Article - Oct 04, 2018 by Verification Horizons
Today, very high expectations are placed on electronic systems in terms of functional safety and reliability. Users expect their planes, automobiles, and pacemakers to work perfectly, and keep on working for years. A reboot of a smartphone is annoying, but rebooting the airplane or car electronics while underway could be catastrophic, and a glitch in an implanted medical device could be life threatening.
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UVM 1800.2 and the New & Improved Cookbook
Resource (Slides) - Sep 27, 2018 by
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A Fresh Look at Creating a UVM Environment - UVM Framework
Resource (Slides) - Sep 27, 2018 by
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A Fresh Look at Creating a UVM Environment - All Slides
Resource (Slides) - Sep 27, 2018 by
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A Fresh Look at Creating a UVM Environment - Introduction
Resource (Slides) - Sep 27, 2018 by
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Vista Virtual Prototyping
Resource (Slides) - Sep 27, 2018 by
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Visualizer Debug Introduction
Resource (Slides) - Sep 27, 2018 by
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UVM 1800.2 & The New and Improved UVM Cookbook
Resource (Slides) - Sep 11, 2018 by Tom Fitzpatrick
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UVM 1800.2 & The New and Improved UVM Cookbook
Webinar - Sep 11, 2018 by Tom Fitzpatrick
This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard.
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UVM
Cookbook - Sep 05, 2018 by Verification Methodology Team
The (2018) version conforms to the IEEE 1800.2 UVM Standard and promotes an emulation-friendly UVM testbench architecture that promotes reuse of your UVM environment as your project moves from simulation to emulation and beyond. Find all the UVM methodology advice you need in this comprehensive and vast collection.
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UVM-2017 v0.9 Library Code for IEEE 1800.2
Resource (Tarball) - Aug 29, 2018 by
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UVM 2017-1.0 Reference Implementation
Resource (Tarball) - Aug 29, 2018 by
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UPF Information Model: The Future of Low-Power Verification Today
Paper - Aug 28, 2018 by Progyna Khondkar
The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.
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UPF Information Model - The Future of Low-Power Verification Today
Resource (Technical Paper) - Aug 28, 2018 by Progyna Khondkar
The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.
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Using Automation to Close the Loop Between Functional Requirements and their Verification
Webinar - Aug 10, 2018 by Brian Craw
This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.