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Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design

Seminar - Mar 31, 2021 by Michael Fingeroff - Siemens EDA

This workshop will show how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It will focus on using the open-source MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator.
Functional Debug: Verification and Beyond

Webinar - Mar 31, 2021 by Hanan Moller

In this session, we will discuss the features of functional debug solutions and the benefits they bring throughout the SoC development process.
Making Your DPI-C Interface a Fast River of Data

Webinar - Mar 31, 2021 by Rich Edelman

This session will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

Webinar - Mar 31, 2021 by Progyna Khondkar

This session distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.
Functional Debug: Verification and Beyond

Webinar - Mar 31, 2021 by Hanan Moller

In this session, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture.
Bringing Reset and Power Domains Together: Confronting Issues Due to UPF Instrumentation

Conference - Mar 31, 2021 by Abdul Moyeen

This session specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.
Making Your DPI-C Interface A Fast River Of Data

Resource (Slides (.PDF)) - Mar 31, 2021 by Rich Edelman

DPI-C is a powerful way to integrate C code with SystemVerilog. The interface is a simple function or task call, identical to a normal SystemVerilog function or task call. This paper will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.
Making Your DPI-C Interface A Fast River Of Data

Resource (Paper (.PDF)) - Mar 31, 2021 by Rich Edelman

SystemVerilog DPI-C enables functional verification teams to leverage C code for modeling, checking and utility functions. The simple "C" style call interface allows fast adoption and easy integration. This paper explains the workings of the integration and provides data type mapping examples and some hints on optimizing the calls for maximum performance.
“Bounded Proof” Sign-Off with Formal Coverage

Webinar - Mar 31, 2021 by Joe Hupcey

In this session, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.
Structural Analysis for Reset-Domain Crossing (RDC) with Set-Reset Flop

Conference - Mar 31, 2021 by Abdul Moyeen

This session specifically explores the different possible scenarios with such flops and problems introduced by these in the Reset-Domain Crossing (RDC) closure. Which potentially can be dangerous and time consuming.
Handling Reset-Domain Crossing for Designs with Set-Reset Flops

Resource (Slides (.PDF)) - Mar 31, 2021 by Abdul Moyeen

There are cases where the Reset-Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design structures where there are more than one asynchronous set/reset controlling a flop. Then there can be scenarios involving data transfer between two such flops. Another matter of concern is if the output of such flops is used as reset further down the design.
Handling Reset-Domain Crossing for Designs with Set-Reset Flops

Resource (Paper (.PDF)) - Mar 31, 2021 by Abdul Moyeen

There are cases where the Reset-Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design features where there is more than one asynchronous set/reset controlling a flop. This paper specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming.
Handling Reset-Domain Crossing for Designs with Set-Reset Flops

Resource (Paper (.PDF)) - Mar 31, 2021 by Abdul Moyeen

Reset-Domain Crossing (RDC) has emerged into a major and un-avoidable design step in modern ASIC design flows. In any Digital design, Reset-Domain Crossing is essentially a structure where a signal crosses over from one reset domain to another reset domain. In this paper we will try to look at the problem structurally and propose a strategy to reach a conclusion where we face such design structures.
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

Resource (Slides (.PDF)) - Mar 31, 2021 by Progyna Khondkar

Top level primary IOs remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications multifold at RTL and gate-level simulations for them.
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

Resource (Paper (.PDF)) - Mar 31, 2021 by Progyna Khondkar

This paper distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.
Bringing Reset and Power Domains Together: Confronting Issues Due to UPF Instrumentation

Resource (Slides (.PDF)) - Mar 31, 2021 by Abdul Moyeen

The Unified Power format (UPF) standard enables designers to add power intent for the design. For power management designers typically partition design into power domains. Interactions between these power domains are done through various power control logics like retention logic, isolation logic, level shifters, etc. Designers need to validate that the power control logic does not introduce new multi-clock and multi-reset issues into the design.
Bringing Reset and Power Domains Together: Confronting Issues Due to UPF Instrumentation

Resource (Paper (.PDF)) - Mar 31, 2021 by Abdul Moyeen

This paper specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.
Functional Debug: Verification and Beyond

Resource (Slides (.PDF)) - Mar 31, 2021 by Hanan Moller

In this session, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture.
I Didn’t Know Visualizer Could Do That

Webinar - Mar 30, 2021 by Rich Edelman

In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.
Preventing Glitch Nightmares on CDC Paths

Webinar - Mar 26, 2021 by Ping Yeung

As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths.
Applying Big Data to Next-Generation Coverage Analysis and Closure

Conference - Mar 26, 2021 by Tom Fitzpatrick

In this session, we will explore new ways of visualizing coverage data from different verification platforms – including simulation, emulation, FPGA and virtual prototyping and formal verification – to facilitate analytical navigation, and applying advanced analytics, including data mining and machine learning, to help your team identify functional coverage holes and effectively mobilize your verification team to reach coverage closure like never before.
The Life of a SystemVerilog Variable

Webinar - Mar 26, 2021 by Dave Rich

This session presents a background on the different categories of variable lifetimes, what their intended use models are, and how improper usage can be corrected.
Preventing Glitch Nightmares on CDC Paths

Resource (Slides (.PDF)) - Mar 26, 2021 by Ping Yeung

As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths.
Bounded Proof Sign-Off with Formal Coverage

Resource (Paper (.PDF)) - Mar 26, 2021 by Joe Hupcey

In this paper, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.
Applying Big Data to Next-Generation Coverage Analysis and Closure

Resource (Slides (.PDF)) - Mar 26, 2021 by Darron May

Coverage closure remains the biggest functional verification challenge in our industry. This two-hour technical presentation will establish the need for a next-generation collaborative verification platform, providing enterprise-wide team-based shared coverage analytics and collaborative verification process integration, including lifecycle management integration.