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Specifying Registers
Chapter - Mar 18, 2018 by Verification Methodology Team
Hardware functional blocks connected to host processors are managed via memory mapped registers.
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Register-Level Functional Coverage
Chapter - Mar 18, 2018 by Verification Methodology Team
The UVM supports the collection of functional coverage based on register state in three ways:
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Testbench Basics
Chapter - Mar 15, 2018 by Verification Methodology Team
Before we can get into discussing the recipes presented in the UVM Cookbook, we have to make sure that we're all talking about the same ingredients. This chapter introduces the UVM concepts that the reader should know in order to understand the recipes presented herein. This section will be incredibly valuable to new UVM users, but experienced UVM users may be able to just straight to the UVM Testbench chapter.
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Interfaces and Virtual Interfaces
Chapter - Mar 15, 2018 by Verification Methodology Team
The SystemVerilog interface provides a convenient means of organizing related signals into a container in order to simplify connections between modules.
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UVM Cookbook
Resource (Cookbook) - Mar 15, 2018 by Verification Methodology Team
The UVM Cookbook conforms to the IEEE 1800.2 UVM Standard and promotes an emulation-friendly UVM testbench architecture that promotes reuse of your UVM environment as your project moves from simulation to emulation and beyond.
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UVM Sequences
Chapter - Mar 15, 2018 by Verification Methodology Team
In testbenches written in traditional HDLs like Verilog and VHDL, stimulus is generated by layers of sub-routine calls which either execute time consuming methods (i.e. Verilog tasks or VHDL processes or procedures) or call non-time consuming methods (i.e. functions) to manipulate or generate data.
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UVM Configuration Database
Chapter - Mar 15, 2018 by Verification Methodology Team
The uvm_config_db is a UVM utility class that is used to pass configuration data objects between component objects in a UVM testbench.
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Handling Parameterization
Chapter - Mar 15, 2018 by Verification Methodology Team
Parameters are commonly used to configure design IP and interfaces. From the perspective of VIP, parameters usually affect the width of bus fields or the number of channels or lanes in use.
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Virtual Interface BFMs
Chapter - Mar 15, 2018 by Verification Methodology Team
In order to make verification components reusable between testbenches they are organized as uvm_agents with an associated signal interface. These are also referred to as UVCs (Universal Verification Components).
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Abstract-Concrete Class Connections
Chapter - Mar 15, 2018 by Verification Methodology Team
An alternative to using a virtual interface handle for DUT to UVM testbench connections is to use an abstract concrete class pair.
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Connecting the Testbench to the DUT
Chapter - Mar 15, 2018 by Verification Methodology Team
Learn all about connecting a DUT to a UVM testbench.
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Messaging in Sequences
Chapter - Mar 12, 2018 by Verification Methodology Team
Sequences typically use messaging, either for debug, traceability or to report on the outcome of a built-in checking mechanism.
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Messaging
Chapter - Mar 12, 2018 by Verification Methodology Team
The UVM messaging system provides an infrastructure for printing messages in a consistent format from a UVM testbench
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UVM Report Catcher
Chapter - Mar 12, 2018 by Verification Methodology Team
There are situations where you may need to change a message generated by the messaging system, and the uvm_report_catcher is built-in call-back mechanism for doing this.
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Command-Line Verbosity Control
Chapter - Mar 12, 2018 by Verification Methodology Team
There are several UVM plusargs that can be used to control messaging verbosity, actions and severity from the command line.
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Testing Message Status
Chapter - Mar 12, 2018 by Verification Methodology Team
At the end of a UVM simulation, the report server issues a messaging summary to the transcript of the simulation.
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Using Messaging
Chapter - Mar 12, 2018 by Verification Methodology Team
The recommended way to use the UVM messaging system is to use the message macros, since they automatically insert the file name and line number of the message source into the UVM message string which is useful for debugging
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Complex Address Maps
Chapter - Mar 09, 2018 by Verification Methodology Team
In SoC design, the address mapping of registers and memory is often more complex than a single map.
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Accellera UVM 1.2 Summary
Chapter - Mar 09, 2018 by Verification Methodology Team
Cookbook topics which link to this page are affected by backwards compatibility issues or migration issues, when the Accellera UVM1.2 release is used
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Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs
Webinar - Mar 07, 2018 by Ellie Burns
In this session, you will be introduced to the tutorial agenda and markets, metrics, dimensions and Lifecyle of low-power design and verification.
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Questa Verification IP Integration
Session - Mar 04, 2018 by Dave Aerne
In this session, you will learn how to integrate Questa Verification IP within your UVMF testbench.
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Questa VIP Integration
Resource (Slides) - Mar 04, 2018 by Dave Aerne
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Understanding the UPF Power Domain and Domain Boundary
Article - Mar 02, 2018 by Progyna Khondkar
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Configuring Memory Read Completions Sent by PCIe® QVIP
Article - Mar 01, 2018 by Arushi Jain, Rajat Rastogi - Siemens EDA
In real hardware systems, the read completion sizes for upstream read requests (initiated towards the root complex) are characteristics of the processor in use and the maximum payload size (request payload size) limitations of endpoint as a receiver. Out of various aspects to be considered while creating a read completion, important aspects of data associated with it are byte enables (valid data to be read), value of the read request, and address at which the request is initiated.
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SATA Specification 3.3 Gaps Filled by SATA QVIP
Article - Mar 01, 2018 by Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens EDA
Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors and mass storage devices. SATA is a high-speed serial protocol with a point-to-point connection between the host and each of its connected devices. It is a layered protocol comprising of a command and application layer, transport layer, link layer, and physical layer.