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Bounded Proof Sign-Off with Formal Coverage

Resource (Paper (.PDF)) - Mar 26, 2021 by Joe Hupcey

When using formal verification on large DUTs, after solving an initial set of provable assertions, it is common to have some remaining assertions which are not proven -- or disproven -- in the course of the analysis. Even though formal couldn’t conclusively verify the expected behavior, the DUT behaviors recorded up until the analysis halted still provides meaningful information.
The Life of a SystemVerilog Variable

Resource (Paper (.PDF)) - Mar 26, 2021 by Dave Rich

Some of the most common issues are how and when variables get initialized, how concurrent threads interact with the same variable, and how certain variable lifetimes interact with other SystemVerilog features in terms of performance considerations. This paper presents a background on the different categories of variable lifetimes, what their intended use models are, and how improper usage can be corrected.
The Life of a SystemVerilog Variable

Resource (Slides (.PDF)) - Mar 26, 2021 by Dave Rich

In software programming, lifetime is defined by when and from where a variable is available for access. This is particularly important when there are multiple process threads with lifetimes of their own trying to access the same variable. A variable becomes a symbolic name for a particular range of memory locations allocated to a specific data type.
Preventing Glitch Nightmares on CDC Paths: The Three Witches

Resource (Slides (.PDF)) - Mar 26, 2021 by
Preventing Glitch Nightmares on CDC Paths: The Three Witches

Resource (Paper (.PDF)) - Mar 26, 2021 by
ModelSim to Questa - Productivity Features

Webinar - Mar 25, 2021 by Jonathan Craft

In this session, you will gain an understanding of the differences between the ModelSim and Questa simulators and will be introduced to the advanced verification techniques and methodology necessary for design and verification of high-end FPGA and ASIC.
Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Webinar - Mar 25, 2021 by Ray Salemi

This session introduces `pyuvm`, a Python implementation of IEEE Spec 1800.2. It discusses the Python tricks used to implement UVM features such as the factory, FIFOs, and config_db.
Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Resource (Slides (.PDF)) - Mar 25, 2021 by Ray Salemi

How does Python drive the simulator? One approach: cocotb
Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Resource (Paper (.PDF)) - Mar 25, 2021 by Ray Salemi

This paper introduces `pyuvm`, a Python implementation of IEEE Spec 1800.2. It discusses the Python tricks used to implement UVM features such as the factory, FIFOs, and config_db.
Spiral Refinement Methodology for Silicon Bug Hunt

Webinar - Mar 24, 2021 by Mark Eslinger

In this session, we capture the refinement process into a step-by-step methodology, formulate it graphically so that it is easy to understand and replicate.
Spiral Refinement Methodology for Silicon Bug Hunt

Resource (Paper (.PDF)) - Mar 24, 2021 by Ping Yeung

This paper will present a "spiral refinement" bug hunt methodology that captures the success factors and guides the deployment of various formal techniques. The objective is to identify the significant challenges and gradually improve each of the factors to "zero-in" on the critical bugs.
Spiral Refinement Methodology for Silicon Bug Hunt

Resource (Slides (.PDF)) - Mar 24, 2021 by Ping Yeung

Several companies have used formal verification to perform silicon bug hunting. That is one of the most advanced usages of formal verification. It is a complex process that includes incorporating multiple sources of information and managing numerous success factors concurrently.
Advance your Designs with Advances in CDC and RDC

Resource (Slides (.PDF)) - Mar 23, 2021 by Kurt Takara

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC.
Advance your Designs with Advances in CDC and RDC

Webinar - Mar 23, 2021 by Kurt Takara

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC.
Cocotb Bus Functional Models

Resource (Verification Horizons Blog) - Mar 22, 2021 by Ray Salemi

How to use cocotb to write bus functional models in Python.
Automatic Formal Verification - Questa Static and Formal Apps

Webinar - Mar 21, 2021 by Walter Gude

In this session, you will gain an understanding of the automatic formal applications that can be used to solve current design and verification challenges.
Introduction to Coroutines

Resource (Verification Horizons Blog) - Mar 11, 2021 by Ray Salemi

Why a Python feature intended for I/O and asynchronous communication is perfect for verification.
Celebrating 10 Years of the UVM

Article - Mar 03, 2021 by Mark Peryer

Version 1.0 of the UVM class library was released by Accellera at the end of February 2011, the result of a unique collaborative effort between fierce competitors (Siemens EDA, formerly Mentor Graphics, Cadence, and Synopsys) and a small number of activist user companies. The objective was to provide an industry standard SystemVerilog based verification methodology.
Purging CXL Cache Coherency Dilemmas

Article - Mar 03, 2021 by Nikhil Jain, Gaurav Manocha - Siemens EDA

The massive growth in the production and consumption of data, particularly unstructured data, like images, digitized speech, and video, results in an enormous increase in accelerators' usage. The growing trend towards heterogeneous computing in the data center means that, increasingly, different processors and co-processors must work together efficiently, while sharing memory and utilizing caches for data sharing.
What is “Verification” in the Context of DO-254 (Avionics) Programs?

Article - Mar 03, 2021 by Michelle Lange, Jeff Reeve and Tammy Reeve - Patmos Engineering Services

If you are a hardware design or verification engineer, you probably have a good idea of what verification entails. However, add compliance to RTCA/DO-254 as a requirement, and suddenly the definition of “verification” may not be so clear. First, the term “verification” must be understood alongside the synergistic term “validation.” Next, in a DO-254 context, verification spans a wider scope than it does traditionally, so understanding this is crucial.
Formal Etiquette for Code Coverage Closure

Article - Mar 03, 2021 by Ajeetha Kumari, Arunachalam R and Satheesh Ethiraj - VerifWorks

Coverage closure is a key step in any IP design verification project. Code coverage is a much-needed metric in most modern-day IP designs. It helps teams to ensure that all RTL code written is indeed exercised and verified prior to tape-out. Without such a guarantee, a semiconductor design house may well be risking millions of dollars in a potential bug-escape to silicon. As the process of code coverage is well automated, it is widely used in the industry.
A Formal Verification Technique for Complex Arithmetic Hardware

Article - Mar 03, 2021 by Dr. Sam Elliott - Imagination Technologies

With more emphasis within the electronics industry on high-performance and shorter time to market, the need for high-confidence and high-quality end-to-end verification is becoming more and more important. This is especially true on the heavily optimized arithmetic datapath blocks most used in modern compute and neural network applications. Missed bugs can delay projects and be costly to reputations, and, at the very least, be likely to sap performance.
Predictable and Scalable End-to-End Formal Verification

Article - Mar 03, 2021 by Dr. Ashish Darbari

In this article, we discuss why formal verification adoption has been limited in industry, and how abstraction-based methodology in formal verification can help DV engineers become successful in adopting formal property checking more widely. Abstraction is the key to obtaining scalability and predictability. It provides an efficient bug-hunting technique and helps in establishing exhaustive proof convergence.
Enabling RISC-V Based System Development

Article - Mar 03, 2021 by Sandeep Nasam, Sagar Thakran - Logic Fruit Technologies

This article focuses on providing a jump start on RISC-V development. It shows how to build a verification environment quickly involving a RISC-V core and required peripherals based on selected applications.
The Six Steps Of RISC-V Processor Verification Including Vector Extensions

Article - Mar 03, 2021 by Larry Lapides

The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench, Tests, Reference model, and Siemens EDA Questa SystemVerilog simulation environment.