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Formal Coverage: An Approach to Analyze Property Holes
Resource (Recording) - Dec 08, 2022 by Aishwarya Sridhar
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Formal Coverage: An Approach to Analyze Property Holes
Resource (Slides) - Dec 08, 2022 by Aishwarya Sridhar
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The X-factors of X-checking
Resource (Slides) - Dec 08, 2022 by Kanthi Palaniappan
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The X-factors of X-checking
Resource (Recording) - Dec 08, 2022 by Kanthi Palaniappan
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Make Formal Simple and Easy-to-Use with Generated Assertion IP
Resource (Slides) - Dec 08, 2022 by Tobias Ludwig - Lubis EDA
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Make Formal Simple and Easy-to-Use with Generated Assertion IP
Resource (Recording) - Dec 08, 2022 by Tobias Ludwig - Lubis EDA
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osmosis 2022
Conference - Dec 08, 2022 by Nicolae Tusinschi
osmosis is about sharing success in using formal techniques to solve verification challenges, and networking with our R&D experts and other attendees.
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Out of the Verification Crisis - Improving RTL Quality
Article - Dec 01, 2022 by Harry Foster
A verification crisis is upon us that will not be solved solely through improvements in verification methodologies and techniques. The solution requires a holistic and philosophical change in the way we approach design with a foundation based on bug prevention. Our proposed first step in implementing this change tightly integrates static analysis into the design process, resulting in a decrease in bug density, which has a positive impact on downstream processes and consequently reduces cost.
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Effective Resource Utilization in PCIe® Gen6: Shared Flow Control
Article - Dec 01, 2022 by Vidushi Goel - Siemens EDA
In PCIe® 6.0, the data rate has doubled from 32 GT/s to 64 GT/s. This technology is a cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data centers, artificial intelligence/machine learning, HPC accelerators, and data center applications like high-end SSDs, automotive, IoT, and military/aerospace, while also maintaining backward compatibility with all previous generations of PCIe.
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Data Integrity through TLP Encryption in PCI Express®
Article - Dec 01, 2022 by Om Prakash - Siemens EDA
In today’s modern era, there has been an increase in the relentless push for higher-speed data transfers along with the security of the data to be transferred. The need for protecting the confidentiality of data is increasing day by day. The need to process higher data bandwidth is catered with the increased speed of PCIe®.
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Missing Your Buttons and Menus? Create Your Own
Article - Dec 01, 2022 by Vishal Baskar
Increasing efficiency while debugging involves having access to the right tools, permissions, and the ability to use the debug tool to its fullest. We know how engineers spend their time debugging rather than verifying. Provide them with all the features of a debugging tool, and they would not have exited the tool while enjoying debugging.
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Application of AI/ML to Optimize Fault Simulation Coverage
Article - Dec 01, 2022 by Avnita Pal and Sastry Puranapanda - Silicon Interfaces®
Fault simulation replicates the typical sources of failures and analyzes them using the leading EDA tool. Testing is structured using fault simulator techniques to gain insight into fault effects and ensure defect coverage and quality testing are achieved. This article is based on standard fault Simulation and standard fault simulation techniques used in industry and applies intelligence and learning algorithms to reduce simulation cycles.
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Understanding and Using Immediate Assertions
Article - Dec 01, 2022 by Ben Cohen
Immediate assertions are typically used to verify that expressions are within their required bounds, such as no overreach of the value of a counter or an illegal condition such a write without an enable. The action block is typically used for debug to display more information as to the cause of the error. However, immediate assertions can also be used to modify testbench variables for use in monitors or in other assertions, or to change the course of a testbench flow.
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Union of SoC Design & Functional Safety Flow
Webinar - Nov 30, 2022 by Vedant Garg
In this session, you will learn how Siemens’ safety verification tools and unique methodologies are easy to adopt, and how they accelerate each development phase.
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Part 7: IC/ASIC Design Trends
Resource (Verification Horizons Blog) - Nov 28, 2022 by Harry Foster
Now my plan is to shift the focus in this series of blogs from FPGA trends to IC/ASIC trends. And specifically in this blog, I present trends related to various aspects of design to illustrate growing design complexity. Fig. 7-1 shows the trends from the 2012 through the 2022 studies in terms of active IC/ASIC design project by design sizes (gates of logic and datapath, excluding memories).
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Part 6: FPGA Language and Library Trends
Resource (Verification Horizons Blog) - Nov 21, 2022 by Harry Foster
In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP. Hence, you might note that the percentage adoption for some of the languages that I present sums to more than one hundred percent.
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Functional Verification Study - 2022
Webinar - Nov 16, 2022 by Harry Foster
In this session, Harry Foster highlights the key findings from the 2022 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
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Part 5: FPGA Verification Technology Adoption Trends
Resource (Verification Horizons Blog) - Nov 13, 2022 by Harry Foster
In this blog I present verification techniques and technologies adoption trends, as identified by the 2020 Wilson Research Group study. An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was about seven years ago in terms of pre-lab verification maturity—and it is catching up quickly. A question you might ask is, “What is driving this trend?”
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Part 4: FPGA Verification Effort Trends (Continued)
Resource (Verification Horizons Blog) - Nov 06, 2022 by Harry Foster
In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time. Verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in fig. 4-1. In 2022, design engineers spent on average 58 percent of their time involved in design activities and 42 percent of their time in verification.
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Questa Design Solutions as a Sleep Aid
Webinar - Nov 02, 2022 by Vinayak Desai
In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
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Questa Design Solutions as a Sleep Aid
Resource (Slides) - Nov 02, 2022 by Vinayak Desai
In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
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Part 3: FPGA Verification Effort Trends
Resource (Verification Horizons Blog) - Oct 30, 2022 by Harry Foster
In this blog I focus on FPGA verification effort trends. Directly asking study participants how much effort they spend in verification will not work. The reason is that it’s hard to find a paper or article on verification that doesn’t start with the phrase: “Seventy percent of a project’s effort is spent in verification…” In other words, the industry is already biased to respond with this effort value. Yet, there are really no creditable references to quantify this value.
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CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
Resource (Slides) - Oct 25, 2022 by Atul Sharma
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
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CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Webinar - Oct 25, 2022 by Atul Sharma
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
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Industry Data and Surveys
Track - Oct 24, 2022 by Harry Foster
Every two years, Siemens EDA commissions Wilson Research Group to conduct a broad, vendor-independent survey of design verification practices around the world. Results of the functional verification study demonstrate an ongoing convergence of design and verification practices toward a common methodology.