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Formal and the Next Normal
Webinar - Oct 19, 2022 by Joe Hupcey
In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.
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Dig a Pool of Specialized SystemVerilog Classes
Resource (Verification Horizons Blog) - Oct 17, 2022 by Chris Spear
SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if you want to reuse the methods but change the type of properties? Use a parameter and specialize it!
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Part 1: The Global FPGA Semiconductor Market
Resource (Verification Horizons Blog) - Oct 16, 2022 by Harry Foster
In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity. The 2021 global semiconductor market was valued at $552.5 billion after experiencing a 24 percent growth over 2020. The FPGA portion of the semiconductor market was valued at about $5.3 billion in 2021. The FPGA semiconductor market is expected to reach a value of $9.3 billion by 2030, growing at a compounded annual growth rate (CAGR) of 6.5 percent during this forecast period.
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UVM Testbench Debug – A Day At The Beach – Right?
Resource (Verification Horizons Blog) - Oct 04, 2022 by Rich Edelman
Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the beach. At my house, summer is definitely over but we’re still getting a declining number of “summer hot” days – without the benefit of the beach. This summer we spent some time doing nothing much at the beach. But it’s hard to shut it all down – I kept thinking about how debug is like a day at the beach…
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Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs
Webinar - Sep 30, 2022 by Martin Rowe
In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.
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Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Webinar - Sep 21, 2022 by Gordon Allan
In this session, we take a look at how to scale your verification capability to match those designs, divide and conquer, and use the right abstractions to equip projects with high quality and faster time-to-market, and to equip design/verification engineers with scalable tools and solutions for verification.
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Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Resource (Slides) - Sep 21, 2022 by Gordon Allan
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM.
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SystemVerilog: Implicit handles
Resource (Verification Horizons Blog) - Sep 06, 2022 by Chris Spear
How can your routine access a class-level variable when there is a local variable with the same name? This often happens when a set() method or the constructor initializes a class property with an argument. A common style is to give the argument the same name as the class property, such as weight shown here. If the assignment was just “weight = weight”, both names would refer to the closest definition, which is the routine argument.
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SystemVerilog: Class Member Visibility
Resource (Verification Horizons Blog) - Aug 29, 2022 by Chris Spear
With most OOP languages, you are encouraged to limit direct access to class members, especially properties (variables), to prevent this sort of bug. The recommendation is to create set() and get() methods. In SystemVerilog, the default access is public, which means that other code can read and write properties and call all methods (routines). There is no keyword for this behavior.
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UVM Framework Release 2022.3
Resource (Tarball) - Aug 15, 2022 by Bob Oden
General Updates: Out of order race scoreboard added to uvmf_base_pkg Added ability to set base class for subset of UVMF base classes using BASE_T parameter Added uvmf_virtual_sequence_base and uvmf_virtual_sequencer_base to uvmf_base_pkg.
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Finding Data
Resource (Verification Horizons Blog) - Jul 28, 2022 by Rich Edelman
Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed). But enough with weeding. What are some debug techniques that I can use in everyday life? In this installment of using Visualizer Debug Environment – “Finding Data” will offer useful debug and visualizations for everyday debug.
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Back to the Future with Formal Property Checking
Article - Jul 05, 2022 by Harry Foster
Back in 2010, I decided that instead of documenting a specific instance of applying formal property checking on a particular design, I would step back and look at the formal property checking process holistically. The goal was to define a set of repeatable steps that could be applied to any design. Fast forward to today, where I update the original by keeping the content that is still relevant and augmenting it with the new philosophies, methodologies, and technologies that have evolved since.
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The Democratization of Digital Methodologies for AMS Verification
Article - Jul 05, 2022 by Sumit Vishwakarma
A mixed-signal design is a combination of tightly interlaced analog and digital circuitry. Next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern systems on chips (SoCs). There are two critical reasons for this trend.
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Getting to Know Visualizer - Part II
Article - Jul 05, 2022 by Rich Edelman
Welcome to part 2 of our overview of the Visualizer Debug Environment, the user interface to debug, analyze and verify all our Siemens functional verification tools. As we saw in part 1 , Visualizer is first and foremost a waveform debugger, with a host of other powerful debug capabilities also provided and supporting Verilog, SystemVerilog, VHDL, System C and C/C++. In this part of the article, we’ll look at driver tracing, X tracing, schematics, glitch debug, low power debug and more.
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Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Article - Jul 05, 2022 by Himani Kaushik - Siemens EDA
Since the advent of digitalization, there has been an exponential growth in the volume of data. With this boost in the amount of data, hard disk drives (HDDs) could not sustain the data transfer rates, leading to bottlenecks in data access. Solid state drives (SSDs) have come to the forefront as a promising solution to our modern-day storage demands. SSDs are constantly evolving with upgrades of their critical components to provide high access speeds.
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Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family
Article - Jul 05, 2022 by Yrjö Keränen - Siemens EDA
Booming worldwide development activities for 5G NR create an increasing need for reference data and signal analysis. Recently launched Veloce X-STEP IQ Toolset (IQT) provides 3GPP compliant test data for radio unit (RU) testing needs. IQT workflow integrates with Siemens EDA tools such as Questa, Veloce and X-STEP. Being a standalone software solution, it is a cost-efficient solution to be installed in multiple workstations.
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Speeding OTN Verification Using Emulation
Article - Jul 05, 2022 by Pradeep Gupta, Saurabh Khaitan - Siemens EDA
In today's connected world, bandwidth requirements have shot up drastically due to the exponential growth in data communication. Optical Transfer Networks (OTN) today are the backbone of the tremendous amount of worldwide internet traffic. The ITU-T standards committee developed the OTN standard to address this data explosion with reliable infrastructure and low transmission costs in the optical world.
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Reflections on Users’ Experiences with SVA - Part II
Article - Jul 05, 2022 by Ben Cohen
During my years of contributions to the Verification Academy SystemVerilog Forum, I have seen many trends in real users’ difficulties in the application of assertions, and misunderstandings of how SVA works. In Part 1 of this article, I addressed the difficulties in expressing requirements for assertions, and clarified some critical SVA concepts concerning terminology, threads, and vacuity.
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Easy Testbench Speedups
Article - Jul 05, 2022 by Eileen Hickey - Doulos Inc.
As a Doulos ‘techie’, I train over 100 engineers in SystemVerilog and UVM each year. I do believe quite soundly, that the effort of simulation verification is an art, supported by the language. So, regardless of the language, I have a ready list of useful testbench coding strategies to achieve faster regression CPU cycle execution. This means more regression tests executed in the same amount of ‘wall-clock’ time!
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Functional Safety Verification Challenges for Automotive ICs
Article - Jul 05, 2022 by Mihajlo Katona - Veriest
In a semiconductor world, functional safety is all about data storage and data movement through the system. Electrical or magnetic interference inside hardware systems can cause a single bit to flip to the opposite state spontaneously. And this is a typical case for random failure, which we desperately need to analyze and see its effects on the functional behavior of the system we are verifying.
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The Path to a Safety Mechanism on an Unsafe PCIe® Sub-Module
Article - Jul 05, 2022 by Avnita Pal - Silicon Interfaces
This article illustrates the implementation of Safety Mechanisms on an unsafe PCIe® sub-module and demonstrates the use of Siemens EDA Austemper tools to generate Alarms for fault list detection and ensure Safety using a Duplication Mechanism.
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Questa Lint vs Formal AutoCheck
Webinar - Jun 15, 2022 by Kevin Campbell
In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.
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Questa Lint vs Formal AutoCheck
Resource (Slides) - Jun 15, 2022 by Kevin Campbell
In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.
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The Three Pillars of Intent-Focused Insight
Webinar - Jun 08, 2022 by Harry Foster
This session reviews the impact of today’s verification crisis, identifies the fundamental problem contributing to this crisis, and then prescribes a solution.
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Advanced Debug Techniques
Track - May 23, 2022 by Rich Edelman
In this track, you will learn how the Visualizer Debug Environment can debug and verify your complex SoCs and FPGAs.