Verification Academy

Topic	Replies	Views	Activity
Interface connection to task compile error SystemVerilog SystemVerilog	1	58	December 2, 2024
Drv.seq_item_port.connect(seqr.seq_item_export); UVM	1	111	July 27, 2024
Urandom_range with small maxval type SystemVerilog SystemVerilog	1	88	July 15, 2024
Uvm_mem_walk_seq with byte addressing on larger bus UVM	0	23	May 11, 2025
How and when to use set_report_severity_id_verbosity? UVM	0	34	March 13, 2025
High level Testbench Architecture for 2-input 2-output crossbar UVM InterviewQuestions	0	51	March 7, 2025
Unexpected output in the division with integral and real numbers SystemVerilog Real-datatypes	3	55	August 21, 2024
Why i got a null item from the tlm port? UVM	0	97	June 24, 2024
How to control the generation of large number of Agents? UVM	0	112	June 18, 2024
Issue with $fwrite string truncation SystemVerilog questasim	2	25	April 26, 2025
VPI printf 4-bit logic type SystemVerilog	1	20	May 22, 2025
Error-[ICTTFC] Incompatible complex type usage UVM	1	41	November 27, 2024
Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit SystemVerilog	0	32	March 19, 2025
Synthesizability of the following code SystemVerilog Verilog , InterviewQuestions , synthesis , synthesizable	0	25	February 12, 2025
Error in : Uart UVM testbench UVM	0	46	October 19, 2024
Facing issue while integrating 2 VIP's SystemVerilog UVM	0	98	August 27, 2024
Clock Inference for unclocked sequence used as event control SystemVerilog SystemVerilog , assertion , SVA , system-verilog-assertion-SVA	0	138	June 15, 2024
Bit Precision used during following assignment SystemVerilog	1	23	June 2, 2025
AXI4 Protocol Issues with QVIP Master/Slave Configuration UVM Questa-QVIPs , Verification-IP , AXI-VIP , uvm-sequence-test	2	28	May 23, 2025
Are package functions synthesizable? Do I need to declare them automatic? SystemVerilog SystemVerilog , packages	1	51	March 10, 2025
Need a fully workable Uvm_param_vif_config_db.tgz example UVM	1	18	February 25, 2025
New variable inside static method SystemVerilog static-method	1	60	August 25, 2024
'a' is an illegal forward reference to a non-scope object declared SystemVerilog questasim-error	1	68	August 21, 2024
Uvm_mem model otp memory UVM	0	17	June 6, 2025
Forcing HDL paths from a uvm_sequence UVM SystemVerilog	0	22	May 11, 2025
Risc v integration with transformer accelerator as a co-processor SystemVerilog	0	26	April 30, 2025
U2U Seminar on Design Patterns May 21st 2025 Announcements UVM	0	22	April 28, 2025
How to Share Information Between Two Passive Agents with Different Interfaces (SPI and LVDS) UVM	0	52	January 25, 2025
How to Selectively skip STS ( RO ) registers in bit_bash UVM UVM , RAL , uvm_reg_bit_bash	0	85	September 19, 2024
Xmvlog: *W,CLKIGN Clock expression ignored on assertion. Using the clock that applies to property SystemVerilog assertion	3	52	September 10, 2024
Why my sub interface master_if cannot be found? UVM	2	24	October 23, 2024
Small typo in the code example of chapter: Testbench Configuration in UVM Cookbook UVM testbench-configuration	0	19	May 25, 2025
UVM tlm port to multiple implementation port connection UVM UVM , tlm	0	24	May 14, 2025
Compiling Accellera Standard IEEE1800.2-2020+ With DPI UVM compiling-uvm	0	24	April 22, 2025
Register value is updated based on handshake on B Channel SystemVerilog assertion , SVA	0	35	February 27, 2025
SVA paper: (intersect) vs (throughout, until, until_with, within) Announcements	0	52	November 29, 2024
Standard for UVM / embedded C/C++ interactions UVM	0	53	October 31, 2024
Want to develop a verification IP environment, where should the composition of the package be placed appropriately? UVM	0	82	July 18, 2024
Uvm qvip axis slave tready delay UVM	1	19	May 30, 2025
Triggering multiple modules inside the SoC SystemVerilog	1	80	August 23, 2024
$fread of partial length of memory moving file pointer full length SystemVerilog	0	27	April 8, 2025
Best way to waive one signal mismatching isolation value versus reset value SystemVerilog Questa-Power-Aware-Simulator , UPF--power-aware , Low-Power--UPF , UPF , Low-Power-Verification , Questa-Power-Aware	0	47	February 13, 2025
Access mirror value of a register which can modify the behaviour of protocol UVM	0	98	June 21, 2024
Cannot use svSetScope to call DPI-C function/task in C++ SystemVerilog SystemVerilog , dpi-c , C	1	56	November 10, 2024
Query regarding witness for vacuosly passing assertions in Formal Verification SystemVerilog assertion , SVA	1	24	June 12, 2025
Why does using a generic interface port (without modports) allow both dut0 and dut1 to drive data and enable without error, while using modports enforces directionality and prevents such assignments? SystemVerilog systemverilog-interface	0	28	March 21, 2025
How to write a coverpoint for same register with multiple uvm_reg_map? UVM	0	22	March 12, 2025
Modelling the register fields via callbacks UVM RAL	0	25	March 7, 2025
Understanding event control and value sampling in systemverilog SystemVerilog Event-Regions	0	31	February 21, 2025
Advanced Highperformance Bus UVM	0	40	February 17, 2025