'a' is an illegal forward reference to a non-scope object declared

SystemVerilog
1

typedef enum logic[3:0] {
a=4’h0,
b=4’h1,
c=4’h2
} def;

class abc;
def def_h;
endclass

‘a’ is an illegal forward reference to a non-scope object declared
‘b’ is an illegal forward reference to a non-scope object declared
‘c’ is an illegal forward reference to a non-scope object declared

Any fix for the above questa sim elab error?

3

Not seeing this error in any tool on EDAplayground.com

Is this a complete example?