I’ve configured a uvm_mem with a 32-bit address bus. When creating the memory map, I specified a chunk size of 4 bytes (.n_bytes(4)) and kept the default byte_addressing.
My assumption is that all memory accesses, whether through the frontdoor or backdoor, treat addresses as byte addresses. This means I need to manually adjust these addresses when interacting with the underlying hardware, for instance, by right-shifting the address by two bits before using VPI functions like uvm_hdl_read/deposit in the backdoor.
I initially tested the setup using the uvm_mem_access_seq. This sequence appears to work correctly because it compares frontdoor and backdoor accesses, and even though it increments the address by 1 in its main loop (0, 1, 2, …), the comparison still validates the overall functionality.
However, I encountered a problem with the uvm_mem_walk_seq. This sequence failed because it attempts to compare the value written to address k-1 with an expected value ~(k-1) & ((1'b1 << n_bits) - 1). This comparison fails because k-1 doesn’t represent a valid starting byte address for a 32-bit word access in my memory configuration.
This leads me to believe that either the default uvm_mem_walk_seq isn’t designed to handle a memory configuration with byte addressing and a memory word width larger than a byte, or I’ve missed some crucial configuration setting in uvm_mem.
Furthermore, my SPI-based frontdoor operates with byte addresses in its requests but effectively ignores the last two address bits on the bus. This is because the underlying memory hardware only supports 32-bit word writes.
Is there a specific uvm_mem configuration option that would allow me to use the uvm_mem_walk_seq correctly with byte addressing while ensuring that the sequence increments addresses in 4-byte steps (0, 4, 8, etc.)?"