If I have something like
module dut;
logic[3:0] a = 4'b1100;
logic[3:0] b, = 4'b1010;
endmodule
module top;
dut d;
endmodule
test.c :
void print_data() {
vpiHandle signalHandle, vh, iteration;
s_vpi_value value;
vh = vpi_handle_by_name("top.d", NULL);
iteration = vpi_iterate(vpiReg, vh); [size=4]--> is vpiReg correct ?[/size]
while ( signalHandle = vpi_scan(iteration)) {
vpi_get_value(signalHandle, &value);
vpi_printf("value of iteration = %04x\n",value.value.integer);
}
}
```verilog
i epxect vpi_printf will print hex value of 4'b1100, and 4'b1010, but i got
value of iteration = 0xb6255cb0
value of iteration = 0xb6255cb0