Unexpected output in the division with integral and real numbers

SystemVerilog
1

Hi,

I’m trying to divide the integer value with the real number and storing it in a real number, but I see a unexpected value.

real c;
real period; //Here period = 8.51

c = (256000/period);
`uvm_info(“C”, $sformatf(“c is %.2f”, c),UVM_LOW)

The expected output : 30082.25
The result it displayed is : 30080.00

Can you pls help me getting the expected output.

2

It would help to show a more complete example. I suspect there is a time precision issue. This works for me

module top;
  import uvm_pkg::*;
  real c;
  real period; //Here period = 8.51
  initial begin
    period = 8.51;
    c = (256000/period);
    uvm_report_info("C", $sformatf("c is %.2f", c),UVM_LOW);
  end
endmodule

Displays:

# UVM_INFO @ 0: reporter [C] c is 30082.26
3

Here, I’m using

timeunit 1ns;
timeprecision 1ns;

4

That is not complete enough. How is period getting its value? Can you display it?