Why does using a generic interface port (without modports) allow both dut0 and dut1 to drive data and enable without error, while using modports enforces directionality and prevents such assignments?

interface myBus;
  logic clk;
  logic rst;
  logic [7:0] data;
  logic enable;

  modport dut0 (input clk, rst, enable, output data);
  modport dut1 (input clk, rst, data, output enable);
endinterface

module dut1 (interface  _if);
  always @(posedge _if.clk or posedge _if.rst) begin
    if (_if.rst) begin
      _if.data <= 8'b0;
      _if.enable <= 1'b0;
    end
    
    else begin
      _if.data <= 8'hAA;
      _if.enable <= 1'b1;
    end
  end
endmodule

module dut0 (interface _if);
  always @(posedge _if.clk or posedge _if.rst) begin
    if (_if.rst) begin
      _if.data <= 8'h0;
      _if.enable <= 1'b0;
    end
    
    else begin
      _if.data <= 8'hAB;
      _if.enable <= 1'b1;
    end
  end
endmodule

`include "interface.sv"
`include "dut0.sv"
`include "dut1.sv"
module tb;
  myBus _if();

  dut0 d0 (._if (_if.dut0));
  dut1 d1 (._if (_if.dut1));

  initial begin
    _if.clk = 0;
    _if.rst = 1;
    #10 _if.rst = 0;
  end

  always #5 _if.clk = ~_if.clk;

  initial begin
    $monitor("Time=%0t | data=0x%h | enable=%b", $time, _if.data, _if.enable);
    #50 $finish;
  end
endmodule

and output of this code
Output : -
Time=0 | data=0x00 | enable=0
Time=15 | data=0xaa | enable=1
$finish called from file “testbench.sv”, line 20.
$finish at simulation time 50

This output i expect also because in generic interface allows dut0 and dut1 take anything to input and output

but in this interface code

module dut0 (myBus _if);
  always @(posedge _if.clk or posedge _if.rst) begin
    if (_if.rst) begin
      _if.data <= 8'h0;
      _if.enable <= 1'b0;
    end
    
    else begin
      _if.data <= 8'hAB;
      _if.enable <= 1'b1;
    end
  end
endmodule

module dut1 (myBus _if);
  always @(posedge _if.clk or posedge _if.rst) begin
    if (_if.rst) begin
      _if.data <= 8'b0;
      _if.enable <= 1'b0;
    end
    
    else begin
      _if.data <= 8'hAA;
      _if.enable <= 1'b1;
    end
  end
endmodule

this is eda link : - EDA Playground

Output : -
Time=0 | data=0x00 | enable=0
Time=15 | data=0xaa | enable=1
$finish called from file “testbench.sv”, line 20.
$finish at simulation time 50

this output i am not expecting i am expecting error(Error-[MPCBD] Modport port cannot be driven
dut0.sv, 5
dut0, “_if.enable”
Port ‘enable’ of modport ‘dut0’ has been restricted as an input port. Input
ports cannot be driven.)
that you can’t assign enable in duto and data in dut1 because they are input in modport.