Hello,
I am during the verification of the big SoC (multiple CPUs and peripherals with the a lot of registers) in the process of the verification of registers together with the team we decided to switch all of the registers with the dummy models (on the register block level) but with the possibility to make them normally works (for the booting purposes), for this we have a special logic field for the enabling the dummy model.
During this process I’ve encountered two problems:
- How to pass the hierarchy info about the dummy models (required for doing the later backdoor in the UVM) to the uvm environment.
- How to trigger the all of the modules to switch to a dummy model (change the value of the enabling signal).
For the first problem I have an idea to make an global uvm_pool which store all of the paths of all models as a keys and then iterate over them in the environment and store them. But I am scared that such global approach would impact performance significantly.
For the second problem I have a three ideas:
- Iterate over all of the paths in the sequence and force enable signal to one using uvm_hdl_force.
- Use existing uvm_pool to send the trigger to the model (polling of the value stored in the pool).
- Use SystemVerilog event or uvm_event to trigger them.
But in all of the solutions I am also scared about the performance, because in two of them I’m using “global” variables.
What would you recommend to use in manner of the performance? Does this kind of global variables impact the performance? (My way of thinking is that when using this kind of variables, simulating tool have to take into account that there is a dependency between multiple modules, so it can’t split it to different threads, but I’m not sure if it’s true).
Best Regards,
Kamil