Xmvlog: *W,CLKIGN Clock expression ignored on assertion. Using the clock that applies to property

SystemVerilog
1

Hi,
I am facing this warning, what can be the issue for this warning or what can be done to resolve this warning.
xmvlog: *W,CLKIGN Clock expression ignored on assertion. Using the clock that applies to property

2

Show the assertion.

3

width_check: assert property( @(negedge tb_clk) min_pulse_width_check(io));

4

width_check: assert property( @(negedge tb_clk) min_pulse_width_check(io));
You’re not showing the property min_pulse_width_check(io).

// If min_pulse_width_check(io) looks some like 
@(posedge sysclk) (clk, v=$realtime) ##1 ...

Then the tool is telling you that Clock expression @(negedge tb_clk) is ignored on the assertion because that outer tb_clk is not used. Instead, the assertion is using the clock that applies to property, which is posedge sysclk.
It’s a warning, something to think about. Some tools may not even bother to give you that warning; it really does not have to.