New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

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Boost Your Verification Productivity with Questa Verification IQ

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Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

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Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

Felipe Schneider

Felipe Schneider is Applications Engineering Manager for team supporting Siemens EDA's IP Validation solutions worldwide. Felipe has contributed in the EDA industry for more than 17 years with mixed R&D and Field Engineering roles. His experience (software engineering and silicon design) spans multiple design disciplines: from automatic layout generation and characterization to logic & physical synthesis, transistor-level STA and finally, how to put it everything together without hurting the tapeout schedule of design team. The latter ultimately landed him at Fractal Technologies, acquired by Siemens in 2021. Felipe holds a B.Eng. in Computer Engineering and a M.Sc. in Computer Science, Microelectronics from Federal University of Rio Grande do Sul, Brazil.

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