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Our remarkable run here in New England continues. The New England Patriots just won their fifth Super Bowl championship. After falling behind 28-3, they staged a record-setting come-back to win in overtime. It was incredibly exciting, and I'm not ashamed to admit that my family and I were literally jumping up and down and screaming when the Patriots scored the winning touchdown. No team had ever come back in a Super Bowl from a deficit of more than ten points, so going by past performances, the Patriots' comeback was "impossible."

My daughter actually turned to me at one point and said, "They're going to lose, aren't they?" I replied that it would require an historic comeback, but I never counted them out. In the end, it took an incredible combination of plays (and, admittedly, some bad decisions by the Falcons) for them to pull it off, but they did it! The emotion of this win is just what we need to keep us warm as we face yet another snowstorm while I write this.

The morning after the victory, Patriots coach Bill Belichick was asked how he felt about the game. After admitting how special the game was and how proud he was of his team, he said something that shows why he's now considered the greatest coach of all time. When asked what his plans were, he said, "As far as I'm concerned, we're now five weeks behind all the other teams in preparing for next season." His constant devotion to preparation, planning, and teaching his players is what sets him apart. While we may not be able to reach that level of focus, we can always try to be better at planning and preparing for success.

In our feature article this issue, my longtime friend and colleague, Siemens EDA Chief Scientist Verification Harry Foster, shares some interesting data from the latest round of his biannual Functional Verification survey in "Will Safety Critical Design Practices Improve First Silicon Success?" After sharing some general data, which shows some counter-intuitive results, Harry does a deeper dive to see what effect verification process maturity and safety critical design practices have on first-pass success. I won't spoil it, but you'll likely be surprised by the results.

Continuing with the theme of safety critical practices, our friends at Optima Design Automation share with us "A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products." As you can imagine, automotive safety verification is especially challenging because the ISO 26262 standard requires ensuring that the design will function safely when exposed to random faults, which obviously can occur in a car whose lifespan can be expected to be up to ten years or more. This article explains the fault-injection problem and how their accelerator can help you satisfy the requirements of the standard on your safety-critical project.

One of the advantages of the Portable Stimulus Standard is its ability to specify SoC-level stimulus scenarios that are often difficult to express with UVM sequences. In "Automating Tests with Portable Stimulus from IP to SoC Level," my colleague — and our resident Portable Stimulus guru — Matthew Ballance introduces some of the concepts and language constructs of the proposed standard. You'll see how the declarative nature of the standard makes it easier to specify complex scenarios for block-level verification and also to combine those into SoC-level scenarios.

Our friends at Logic Fruit Technologies next share a few "UVM Tips and Tricks" with you. Whether you're new to UVM or an "old hand," I'm sure you'll find these suggestions useful. It's always helpful to re-examine some of the things we've been doing and see if there's a better way.

Next, another Siemens EDA colleague, Progyna Khondkar, shows how you can take advantage of "Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation." UPF allows you to bind checkers to your design that the Questa® PA-SIM simulator can use to access your UPF supply network and other objects to make sure that your power control is behaving correctly.

We wrap up this issue with "Complementing Functional Verification Through the Use of Available Timing Information" from our friends at Excellicon. We spend much of our time focusing on functional verification, but in this article you'll learn how to use their Constraints Manager tool to extract timing constraints from the design and use them to verify things like clock-domain crossings and timing exceptions. Bringing timing information into the verification process earlier in the development cycle makes everyone more productive.

If you're reading this introduction at DVCon US, please make sure to stop by the expanded Siemens EDA booth and say hi. This year, I'm also the Technical Program Chair, which means I'll get to wear my Patriots shirt on stage during the Opening Session, among other things. If you're an Atlanta Falcons fan, I promise to be gentle. Hope to see you there.

Respectfully submitted,

Tom Fitzpatrick
Editor, Verification Horizons