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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2015 - Volume 11 Issue 2 (11)

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June 2012 - Volume 8 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

Floating-Point Units (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

Messaging (8)

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Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

LLMs (7)

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March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

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November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Objections (7)

Order Property Pattern (7)

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VA Live 2023 - Huntsville (7)

AEH (6)

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Appendix (6)

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Creating and Using a Test Plan (6)

DAC 2018 (6)

DDR (6)

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December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Design Constraints (6)

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Front and Back Door (6)

HDL (6)

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June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MBIST (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

PCIe Gen 7 (6)

Power Efficiency (6)

Pre-Silicon (6)

Prototyping (6)

Random Faults (6)

Respins (6)

Slave (6)

Stimulus Free Verification (6)

Transaction-Level (6)

UCIe 3.0 (6)

UVM Forum (6)

UVVM (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VHDL Testbench (6)

Verbosity (6)

Verification Effectiveness (6)

Visualization (6)

Windows (6)

X-Effects (6)

YAML (6)

osmosis 2024 A&D (6)

Adaptive (5)

Advance Your Verification Methodology (5)

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BIST (5)

Base Class (5)

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Constraint Solver (5)

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DAC 2024 (5)

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Data Encryption (5)

December 2019 - Volume 15 Issue 3 (5)

Defect Coverage (5)

Design Cycle (5)

Design Scaling (5)

Dual Domains (5)

Error (5)

Exhaustive (5)

FMEDA (5)

February 2019 - Volume 15 Issue 1 (5)

Formal Testbench (5)

HBM4 (5)

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Hardware-Assisted Verification (5)

Hierarchical Data Model (5)

High-Speed (5)

IDE (5)

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Instance (5)

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Low Latency (5)

Low Power Verification Forum (5)

MARLUG 2024 (5)

MARLUG 2025 (5)

March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

NVM Express (5)

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Precedence (5)

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Quirky (5)

Repository (5)

SSD (5)

SVUnit (5)

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Simulink (5)

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State-Based Model (5)

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Static RDC (5)

Stimulus Pattern (5)

Tessent Test Solutions (5)

Test Class (5)

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Threads (5)

Transaction-Based Acceleration (5)

VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

VA Live 2024 - Huntsville (5)

VA Live 2024 - Westford (5)

VA Live 2025 - Silicon Valley (5)

VA Live 2026 - El Segundo (5)

Verbose (5)

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5G (4)

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Bit Width (4)

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C++ (4)

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Context-Aware Debug (4)

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DVFS (4)

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Deprecated (4)

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Enumeration (4)

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HBM (4)

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IC Design (4)

ICE Mode (4)

IEEE (4)

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In-Circuit Simulation (4)

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Initial States (4)

LFM (4)

Large Language Models (4)

MCPs (4)

Mathworks (4)

Metastability Injection (4)

Mitigation Architecture (4)

Non-Reset (4)

November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

Partitioning (4)

Phase Objections (4)

Phases (4)

Plusargs (4)

Protocol Checkers (4)

QEMU (4)

QoR (4)

Questa Design Solutions (4)

RTL Verification (4)

Race Conditions (4)

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SFV (4)

SVTB (4)

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Syntax (4)

Tcl/Tk (4)

Test Ranking (4)

Time Cone (4)

Trust Verification (4)

UART (4)

UEC (4)

UPF 4.0 (4)

USB (4)

Unified Coverage Database (4)

Unreachability (4)

Use Models (4)

Utilization (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

VA Live 2026 - Silicon Valley (4)

Vectors (4)

Verification Models (4)

Verification Success (4)

Verification Workflow (4)

X-Aware (4)

$display (3)

1.2 (3)

AHB (3)

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Airborne Electronic Hardware (3)

Analysis Components (3)

Analysis Port (3)

Application Lifecycle Management (3)

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Autonomous Systems (3)

BISR (3)

Base Test (3)

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Boolean (3)

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Built-In Self-Test (3)

CDC Signals (3)

CSI-2 (3)

Case Statements (3)

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Certification (3)

Class Variables (3)

Clocking (3)

Code Quality (3)

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Coroutines (3)

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Cryptography (3)

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Delay Loops (3)

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Domain Specific Architectures (3)

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ESL (3)

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Fibre Channel (3)

GPU (3)

Golden Model (3)

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Handles (3)

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Horizontal Reuse (3)

Illegal Bins (3)

Integrity Challenges (3)

Intelligent Integration (3)

JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

LRM (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

MC2 (3)

MUX (3)

Mailboxes (3)

Mathematical Analysis (3)

Memory Debug (3)

NRRs (3)

NoC (3)

OSVVM (3)

Observer (3)

Open Architecture (3)

PCI-SIG (3)

PHY (3)

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Parallel Computing (3)

Phase-Level (3)

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Power Architecture (3)

Power Gating (3)

Profiling (3)

Protocol Layers (3)

QFL (3)

Qrun (3)

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RISC-V Verification Interface (3)

RTL Emulation (3)

Radiation Mitigation (3)

Re-targeting (3)

Real Number Modeling (3)

Reconfiguration (3)

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Routines (3)

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Stream (3)

TBX (3)

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Test Plan (3)

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Toolkit (3)

Transfer Protocols (3)

Transitive (3)

Type Casting (3)

UEFI (3)

UVM 1.1d (3)

UVM 1.2 (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

UVMC 2.3.2 (3)

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Unidirectional (3)

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VHDL-2019 (3)

VIP - 3.1 (3)

VbyOne (3)

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X-State (3)

2D/3D (2)

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D-PHY (2)

DFT Architecture (2)

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DPPM (2)

DVCON 2021 (2)

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Data Mux (2)

Dead Code (2)

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ECUs (2)

ENV Package (2)

Elements List (2)

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False Path (2)

Fault Model (2)

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Floating-Point Hardware (2)

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GLS (2)

GOMACTech (2)

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Governance (2)

Graph-Based Stimulus (2)

HSI (2)

HVL (2)

Hallucination (2)

Hardening (2)

Hardware / Software (2)

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Heterogeneous (2)

Hole Analysis (2)

Hybrid Virtual Platform (2)

IEEE 754 (2)

IP-XACT (2)

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Intelligent Testbench Automation (2)

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October 2012

Improving Analog/Mixed-Signal Verification Productivity
Analog Mixed-Signal Oct 01, 2012 Ahmed Eisawy Article
VHDL-2008: Why It Matters
VHDL 2008 Oct 01, 2012 Jim Lewis Article
Verification Horizons - Volume 8, Issue 3
Standards Oct 01, 2012 Tom Fitzpatrick pdf

September 2012

UVM 1.1c Class Reference
UVM - Universal Verification Methodology Sep 19, 2012 html
More About UVM Registers
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Protocol Layering in UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Introduction to UVM Registers
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
C-Based Stimulus for UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
UVM Debug
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
UVM Scoreboarding and Results Prediction
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
OVM to UVM Migration
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Customization in UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Improving FPGA Debugging with Assertions
FPGA Verification Sep 10, 2012 Harry Foster Article
UVM Connect 2.2 Kit
UVMC Sep 07, 2012 John Stickley tar

August 2012

FPGA Verification Capabilities
FPGA Verification Aug 30, 2012 Ray Salemi Track
Introduction from Harry Foster
FPGA Verification Aug 30, 2012 Harry Foster Session
Overview and Welcome
FPGA Verification Aug 30, 2012 Ray Salemi Session
Code Coverage
FPGA Verification Aug 30, 2012 Ray Salemi Session
Test Planning
FPGA Verification Aug 30, 2012 Ray Salemi Session
Applied Assertions
FPGA Verification Aug 30, 2012 Ray Salemi Session
Transactions
FPGA Verification Aug 30, 2012 Ray Salemi Session
Self-Checking Testbenches
FPGA Verification Aug 30, 2012 Ray Salemi Session
Automatic Stimulus
FPGA Verification Aug 30, 2012 Ray Salemi Session
Functional Coverage
FPGA Verification Aug 30, 2012 Ray Salemi Session