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November 2018 - Volume 14 Issue 3 (4)

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July 2023 - Volume 19 Issue 2 (3)

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January 2013

Modeling Abstraction
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
AMS Engines
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Overview to Improve AMS Performance
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
VHDL-2008 Overview
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Testbench Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
RTL Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Operator Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Package Type Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Fixed Point Package
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Floating Point Package
VHDL 2008 Jan 18, 2013 Jim Lewis Session
VHDL-2008 Why It Matters
VHDL 2008 Jan 17, 2013 Jim Lewis Track

November 2012

Effectively Modeling and Analyzing Coverage
Coverage Nov 15, 2012 Tom Fitzpatrick Webinar

October 2012

ST-Ericsson Speeds Time to Functional Verification Closure with Questa
Verification IQ Oct 01, 2012 Rachida El Idrissi - St-Ericsson Article
The Top Five Formal Verification Applications
Formal Verification Oct 01, 2012 Roger Sabbagh - Siemens Eda Article
Three Steps to Unified SoC Design and Verification
UVMC Oct 01, 2012 Mark Peryer Article
Evolution of UPF: Getting Better All the Time
Low Power Oct 01, 2012 Erich Marschner Article
Improving Analog/Mixed-Signal Verification Productivity
Analog Mixed-Signal Oct 01, 2012 Ahmed Eisawy Article
VHDL-2008: Why It Matters
VHDL 2008 Oct 01, 2012 Jim Lewis Article
Verification Horizons - Volume 8, Issue 3
Standards Oct 01, 2012 Tom Fitzpatrick pdf

September 2012

UVM 1.1c Class Reference
UVM - Universal Verification Methodology Sep 19, 2012 html
More UVM Registers
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Protocol Layering
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Introduction to UVM Registers
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
C-Based Stimulus for UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
UVM Debug
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

UALink VIP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

osmosis Europe 2025

Thursday, October 16th, 2025 - Munich, DE

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

Browse all content in Siemens Verification Academy with the tag object oriented programming

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