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February 2011

Metastability Verification Flow
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Modeling Metastability
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Integrating CDC Into A Flow
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
H/W-Assisted Testbench Acceleration
Acceleration Feb 25, 2011 Hans Van Der Schoot Session
Testbench Acceleration Depicted
Acceleration Feb 25, 2011 Hans Van Der Schoot Session
Modeling for Acceleration
Acceleration Feb 25, 2011 Hans Van Der Schoot Session
Testbench Acceleration Flow
Acceleration Feb 25, 2011 Hans Van Der Schoot Session
Why Plan?
Planning, Measurement and Analysis Feb 25, 2011 Peet James Session
Why It's Hard
Planning, Measurement and Analysis Feb 25, 2011 Peet James Session
Plan of Attack
Planning, Measurement and Analysis Feb 25, 2011 Peet James Session
SystemVerilog Concurrent Assertions
SystemVerilog Feb 25, 2011 Cliff Cummings Webinar
SystemVerilog Testbench Acceleration
Acceleration Feb 25, 2011 Hans Van Der Schoot Track
Introduction to the Verification Academy
Planning, Measurement and Analysis Feb 25, 2011 Harry Foster Session
Verification Planning and Management
Planning, Measurement and Analysis Feb 22, 2011 Peet James Track

February 2010

Assertion-Based Verification
Assertions Feb 10, 2010 Harry Foster Track
Introduction to Assertion-Based Verification
Assertions Feb 10, 2010 Harry Foster Session
Maturing ABV Process Capabilities
Assertions Feb 10, 2010 Harry Foster Session
Introduction to SystemVerilog Assertions
Assertions Feb 10, 2010 Harry Foster Session
Introduction to Open Verification Library (OVL)
Assertions Feb 10, 2010 Harry Foster Session
Assertion Patterns
Assertions Feb 10, 2010 Harry Foster Session
Cookbook Examples
Assertions Feb 10, 2010 Harry Foster Session
ABV and Formal Property Checking
Assertions Feb 10, 2010 Harry Foster Session
Questa Simulation
Assertions Feb 10, 2010 Chuck Seeley Demo
Questa Formal Verification
Assertions Feb 10, 2010 Mark Eslinger Demo

January 2010

Industry Perspective & Opportunities in ABV
Assertions Jan 15, 2010 Harry Foster Webinar

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Formal Security Webinar

Explore How to Protect Against Data Corruption with Formal Security Verification

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Browse all content in Siemens Verification Academy with the tag Emulation

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