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February 2013 - Volume 9 Issue 1 (8)

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June 2019 - Volume 15 Issue 2 (6)

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Metric Validation (6)

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December 2019 - Volume 15 Issue 3 (5)

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March 2018 - Volume 14 Issue 1 (5)

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VA Live 2019 - Westford (5)

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November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

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USB (4)

UVM 1.1d (4)

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VA Live 2023 - Austin (4)

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1.2 (3)

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July 2023 - Volume 19 Issue 2 (3)

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November 2016

24x7 Productivity: Veloce® Enterprise Server App Does the Job
Acceleration Nov 07, 2016 Vijay Chobisa Article
Power Aware Libraries: Standardization and Requirements for Questa Power Aware
Low Power Nov 07, 2016 Progyna Khondkar Article
Improving Performance and Verification of a System Through an Intelligent Testbench
Simulation Nov 07, 2016 Umesh Patel, Dhaval Shah - Arastu Systems Pvt. Ltd. Article

October 2016

Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Oct 31, 2016 Harry Foster link
Functional Verification Study - 2016
Planning, Measurement and Analysis Oct 14, 2016 Harry Foster Session
Part 9: IC/ASIC Verification Technology Adoption Trends
Planning, Measurement and Analysis Oct 10, 2016 Harry Foster link
Part 8: IC/ASIC Resource Trends
Planning, Measurement and Analysis Oct 04, 2016 Harry Foster link

September 2016

Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Sep 25, 2016 Harry Foster link
Part 6: FPGA Verification Language and Library Adoption Trends
Planning, Measurement and Analysis Sep 21, 2016 Harry Foster link
Part 5: FPGA Verification Technology Adoption Trends
Planning, Measurement and Analysis Sep 11, 2016 Harry Foster link
Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy
UVM - Universal Verification Methodology Sep 09, 2016 Gordon Allan Webinar
Part 4: FPGA Verification Effectiveness Trends
Planning, Measurement and Analysis Sep 07, 2016 Harry Foster link

August 2016

Part 3: FPGA Verification Effort Trends (Continued)
Planning, Measurement and Analysis Aug 29, 2016 Harry Foster link
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Clock-Domain Crossing Aug 26, 2016 Kurt Takara Paper
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Clock-Domain Crossing Aug 26, 2016 Kurt Takara pdf
Extending a Traditional VIP to Solve PHY Verification Challenges
Verification IP Aug 26, 2016 pdf
Total Recall - What to Look for in a Memory Model Library
Verification IP Aug 24, 2016 pdf
SystemVerilog Code Examples
SystemVerilog Aug 24, 2016 Ray Salemi zip
Article: How to instrument your design with simple SystemVerilog assertions
Standards Aug 24, 2016 link
SystemVerilog & UVM Coding & Performance Guidelines
SystemVerilog Aug 24, 2016 pdf
Technical Paper: A Scalable Approach for TLM Across SystemC and SystemVerilog
Standards Aug 24, 2016 pdf
Technical Paper: Towards an Object-Oriented Design Methodology Using SystemVerilog
Standards Aug 24, 2016 pdf
SystemVerilog Performance Guide
SystemVerilog Aug 24, 2016 pdf
SystemVerilog Assertions Design Tricks & SVA Bind Files (slide set 4)
Standards Aug 24, 2016 pdf
SystemVerilog Coding Guide
SystemVerilog Aug 24, 2016 pdf

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November 2016

24x7 Productivity: Veloce® Enterprise Server App Does the Job

Power Aware Libraries: Standardization and Requirements for Questa Power Aware

Improving Performance and Verification of a System Through an Intelligent Testbench

October 2016

Part 10: IC/ASIC Language and Library Adoption Trends

Functional Verification Study - 2016

Part 9: IC/ASIC Verification Technology Adoption Trends

Part 8: IC/ASIC Resource Trends

September 2016

Part 7: IC/ASIC Design Trends

Part 6: FPGA Verification Language and Library Adoption Trends

Part 5: FPGA Verification Technology Adoption Trends

Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy

Part 4: FPGA Verification Effectiveness Trends

August 2016

Part 3: FPGA Verification Effort Trends (Continued)

Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

Extending a Traditional VIP to Solve PHY Verification Challenges

Total Recall - What to Look for in a Memory Model Library

SystemVerilog Code Examples

Article: How to instrument your design with simple SystemVerilog assertions

SystemVerilog & UVM Coding & Performance Guidelines

Technical Paper: A Scalable Approach for TLM Across SystemC and SystemVerilog

Technical Paper: Towards an Object-Oriented Design Methodology Using SystemVerilog

SystemVerilog Performance Guide

SystemVerilog Assertions Design Tricks & SVA Bind Files (slide set 4)

SystemVerilog Coding Guide