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June 2017

Memory Leak Debug
UVM - Universal Verification Methodology Jun 14, 2017 Tom Kiley pdf
Memory Leak Debug
UVM - Universal Verification Methodology Jun 14, 2017 Tom Kiley Session
UVM Configuration Database Debug
UVM - Universal Verification Methodology Jun 14, 2017 Tom Kiley pdf
UVM Configuration Database Debug
UVM - Universal Verification Methodology Jun 14, 2017 Tom Kiley Session
Enterprise Ethernet PHY Verification
Verification IP Jun 13, 2017 Akshay Sarup Webinar
Need for Speed - PCIe® GEN4 Verification
Verification IP Jun 13, 2017 Akshay Sarup Webinar
Creating a Thorough Verification Environment in Less Than Two Days
Verification IP Jun 13, 2017 Jason Polychronopoulos Webinar
Trends and Requirements in High Speed Interface Verification
Verification IP Jun 13, 2017 Niraj Mathur Webinar
MIPI® CSI-2 TX Verification
Verification IP Jun 13, 2017 Ivan Ristic Webinar
Leveraging the latest DDR & Flash Memory Models
Verification IP Jun 13, 2017 Jason Polychronopoulos Webinar
USB 3.1 Verification Challenges
Verification IP Jun 13, 2017 Dinesh Tyagi Webinar
Conquering the New IP Economy
Planning, Measurement and Analysis Jun 13, 2017 Harry Foster Webinar

May 2017

SoC Verification with the Questa Flow
FPGA Verification May 17, 2017 Gordon Allan Webinar

April 2017

Hardware Emulation: Three Decades of Evolution
Simulation Apr 12, 2017 Verification Horizons Article
Sometimes the Life of a College Student and a Verification Engineer Aren’t All That Different
Simulation Apr 10, 2017 Verification Horizons Article

March 2017

Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Low Power Mar 20, 2017 Progyna Khondkar Paper
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Low Power Mar 20, 2017 Progyna Khondkar pdf
Testbench Automation - Environment
UVM Framework Mar 17, 2017 Bob Oden Webinar
Testbench Automation - Introduction
UVM Framework Mar 17, 2017 Bob Oden Webinar
Testbench Automation - Testbench
UVM Framework Mar 17, 2017 Matthew Ballance Webinar
Testbench Automation - Interfaces
UVM Framework Mar 17, 2017 Bob Oden Webinar
Use Formal to Check Logic Faults
Formal Verification Mar 17, 2017 Mark Eslinger Webinar
Will Safety Critical Design Practices Improve First Silicon Success?
Functional Safety Mar 10, 2017 Harry Foster Article
UVM Tips and Tricks
Standards Mar 07, 2017 Verification Horizons Article

February 2017

Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation
Low Power Feb 28, 2017 Progyna Khondkar Article

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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