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November 2018 - Volume 14 Issue 3 (4)

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July 2023 - Volume 19 Issue 2 (3)

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UVM 1.1d (3)

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Transmitter IP (2)

Transport Layer (2)

Trend Analysis (2)

UCIS (2)

Ultra Accelerator Link (2)

Universal Approximation (2)

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February 2019

UVM IEEE Shiny Object
UVM - Universal Verification Methodology Feb 28, 2019 Rich Edelman pdf
The Missing Link: The Testbench to DUT Connection
SystemVerilog Feb 28, 2019 Dave Rich pdf
The Missing Link: The Testbench to DUT Connection
SystemVerilog Feb 28, 2019 Dave Rich Paper
Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Clock-Domain Crossing Feb 28, 2019 Ping Yeung Paper
Clock-Domain Crossing (CDC) Challenges in Latch Based Designs
Clock-Domain Crossing Feb 28, 2019 Kurt Takara pdf
Clock-Domain Crossing (CDC) Challenges in Latch-Based Designs
Clock-Domain Crossing Feb 28, 2019 Kurt Takara Paper
Low Power Apps: Shaping the Future of Low Power Verification
Low Power Feb 28, 2019 pdf
Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Clock-Domain Crossing Feb 28, 2019 Ping Yeung pdf
Formal Techniques for Optimizing ISO 26262 Fault Analysis
Functional Safety Feb 28, 2019 Doug Smith pdf
Using Strong Types in SystemVerilog Design and Verification Environments
SystemVerilog Feb 28, 2019 Dave Rich pdf
Ten Rules to Successfully Deploy Formal
Formal Verification Feb 25, 2019 Dr. Ashish Darbari Article
Formal Apps Take the Bias Out of Functional Verification
Formal Verification Feb 25, 2019 Bill Au Article
Simplifying Assertion Validation Using UVM Callbacks
Assertions Feb 25, 2019 Arushi Jain - Siemens Eda Article
Effective Elements Lists and the Transitive Nature of UPF Commands
Low Power Feb 25, 2019 Progyna Khondkar Article
Selecting a Portable Stimulus Application Focal Point
Portable Stimulus Feb 25, 2019 Matthew Ballance Article
Choosing a Format for the Portable Stimulus Specification
Portable Stimulus Feb 22, 2019 Matthew Ballance pdf
Low Power Verification Forum
Low Power Feb 05, 2019 Gordon Allan Webinar

January 2019

Industry Advancements Required to Close the Power Management Verification Gap
Low Power Jan 28, 2019 Sriram Hariharan Webinar
Deploying A Metrics Driven Low Power Methodology for Your RTL IP
Low Power Jan 28, 2019 Qazi Ahmed Webinar
Low Power Verification & Analysis with Emulation
Low Power Jan 28, 2019 Shantanu Samant Webinar
Productive Low Power Debug Across All Engines and Flows
Debug Jan 28, 2019 Gordon Allan Webinar
Accelerating Verification through Verification IP, Configurator and UVM Framework
Verification IP Jan 24, 2019 Sharath Kannareddy pdf
Making Verification Fun Again
UVM Framework Jan 24, 2019 Jonathan Craft pdf
Verification Acceleration for FPGA Designs with Matlab
Acceleration Jan 24, 2019 Jerry Grula - Siemens Eda pdf
Welcome & Overview
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

HLS Webinar

Wednesday, Nov 05th-8:00 AM PST

Formal Verification of Synthesizable C++/SystemC Designs

VHDL Webinar

Wednesday, Nov 12th-8:00 AM PST

Don't Let VHDL Debugging Slow You Down! Use Questa One Sim

User2User

Nov. 19th | 0800 - 1630 US/Eastern

Mid-Atlantic 2025 | Johns Hopkins University | Laurel, Maryland

Debug Webinar

Wednesday, Dec 03rd-8:00 AM PST

VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim

Verification Academy Live

Scottsdale, AZ | Dec. 3rd - 9:30 - 5:00 US/MST | Top Golf

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