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September 2021 - Volume 17 Issue 2 (12)

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July 2022 - Volume 18 Issue 2 (10)

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June 2012 - Volume 8 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

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June 2016 - Volume 12 Issue 2 (8)

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Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

LLMs (7)

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March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

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Metastable (7)

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November 2014 - Volume 10 Issue 3 (7)

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Order Property Pattern (7)

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VA Live 2023 - Huntsville (7)

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December 2017 - Volume 13 Issue 3 (6)

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June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

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March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

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Open Source (6)

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VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

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VA Live 2025 - Huntsville (6)

Validation (6)

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ATPG (5)

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December 2019 - Volume 15 Issue 3 (5)

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February 2019 - Volume 15 Issue 1 (5)

Flip-Flop (5)

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March 2018 - Volume 14 Issue 1 (5)

Non-Determinism (5)

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UCIe 3.0 (5)

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VA Live 2019 - Westford (5)

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IEEE (4)

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November 2018 - Volume 14 Issue 3 (4)

PCIe Gen 6 (4)

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1.2 (3)

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July 2023 - Volume 19 Issue 2 (3)

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Stream (3)

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TBX (3)

Test Coverage (3)

Test Realization (3)

Transfer Protocols (3)

Trust Verification (3)

Type Casting (3)

UVM 1.1d (3)

UVM 1.2 (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

UVMC 2.3.2 (3)

UVMC 2.3.3 (3)

UVMC 2.3.4 (3)

UVVM (3)

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VHDL-2019 (3)

VIP - 3.1 (3)

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CSI (2)

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SATA (2)

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Stimulus Free Verification (2)

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Test Loading (2)

Thread Control (2)

Throughout (2)

Timing Integrity (2)

Transaction Layer (2)

Transmitter IP (2)

Transport Layer (2)

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May 2021

Advanced UVM
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Track
The Three Witches: Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing May 18, 2021 Ping Yeung Paper
The Three Witches: Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing May 18, 2021 Ping Yeung pdf
Machine Learning at the Edge: Using HLS to Optimize Power and Performance
Machine Learning May 12, 2021 Michael Fingeroff - Siemens Eda pdf
Formal 101: Setting Up & Optimizing Constraints
Formal Verification May 10, 2021 Mark Eslinger Session
Setting Up & Optimizing Constraints
Formal Verification May 10, 2021 pdf
Optimizing a Fault Campaign for Complex Mixed-Signal Devices
Functional Safety May 04, 2021 Jake Wiltgen Webinar

April 2021

Low Power Considerations for Verification
Low Power Apr 29, 2021 Rick Koster Webinar
Formal 101: Basic Abstraction Techniques
Formal Verification Apr 21, 2021 Jin Hou Session
A Methodology for Comprehensive CDC+RDC Analysis
Clock-Domain Crossing Apr 20, 2021 Kurt Takara pdf
A Methodology for Comprehensive CDC+RDC Analysis
Reset-Domain Crossing Apr 20, 2021 Kurt Takara Webinar
Easy Test Writing with a Proxy-driven Testbench
SystemVerilog Apr 06, 2021 Ray Salemi Webinar

March 2021

Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Verification IP Mar 31, 2021 link
Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Verification IP Mar 31, 2021 pdf
Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology
High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda pdf
Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design
High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda Seminar
Functional Debug: Verification and Beyond
Debug Mar 31, 2021 Hanan Moller Webinar
Making Your DPI-C Interface a Fast River of Data
SystemVerilog Mar 31, 2021 Rich Edelman Webinar
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Low Power Mar 31, 2021 Progyna Khondkar Webinar
Functional Debug: Verification and Beyond
Debug Mar 31, 2021 Hanan Moller Webinar
Bringing Reset and Power Domains Together: Confronting Issues Due to UPF Instrumentation
Low Power Mar 31, 2021 Abdul Moyeen Conference
Making Your DPI-C Interface A Fast River Of Data
SystemVerilog Mar 31, 2021 Rich Edelman pdf
Making Your DPI-C Interface A Fast River Of Data
SystemVerilog Mar 31, 2021 Rich Edelman pdf
“Bounded Proof” Sign-Off with Formal Coverage
Formal Verification Mar 31, 2021 Joe Hupcey Webinar
Structural Analysis for Reset-Domain Crossing (RDC) with Set-Reset Flop
Reset-Domain Crossing Mar 31, 2021 Abdul Moyeen Conference

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

VHDL Webinar

Wednesday, Nov 12th-8:00 AM PST

Don't Let VHDL Debugging Slow You Down! Use Questa One Sim

User2User

Nov. 19th | 0800 - 1630 US/Eastern

Mid-Atlantic 2025 | Johns Hopkins University | Laurel, Maryland

Debug Webinar

Wednesday, Dec 03rd-8:00 AM PST

VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim

Verification Academy Live

Scottsdale, AZ | Dec. 3rd - 9:30 - 5:00 US/MST | Top Golf

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

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Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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