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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2015 - Volume 11 Issue 2 (11)

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July 2022 - Volume 18 Issue 2 (10)

June 2013 - Volume 9 Issue 2 (10)

LLMs (10)

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1800.2 (9)

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June 2012 - Volume 8 Issue 2 (9)

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June 2018 - Volume 14 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

Guidelines (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

OSCI (8)

OVM2UVM (8)

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PHY (8)

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UCIe 2.0 (8)

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XML (8)

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ADAS (7)

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Bind (7)

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Connecting the Testbench to the Design (7)

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Execution Semantics and Synchronization (7)

Fabric (7)

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Front and Back Door (7)

GPU (7)

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ISA (7)

Instance (7)

Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

Layering (7)

MCPs (7)

March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

Non-Determinism (7)

November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Order Property Pattern (7)

Parameterized Tests (7)

Post-silicon Debug (7)

Power Estimation (7)

Predictors (7)

Property Analysis (7)

Sequential Analysis (7)

Siemens EDA (7)

Supply Network (7)

Syntax (7)

Testbench Customization in UVM (7)

Tool Qualification (7)

UVVM (7)

Unified Coverage Database (7)

VA Live 2023 - Huntsville (7)

Verbosity (7)

Verification Models (7)

Verification Quality (7)

Verification Workflow (7)

X-Effects (7)

AEH (6)

Address Mapping (6)

Appendix (6)

Artificial Neural Network (6)

Bandwidth (6)

Bugged Out Podcast (6)

Clock Propagation (6)

Concurrent Processes (6)

Coverage Holes (6)

Coverage Intent (6)

Coverpoint (6)

Creating and Using a Test Plan (6)

DAC 2018 (6)

Data Link (6)

December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Defect Coverage (6)

Design Assurance (6)

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Design Scaling (6)

Development Environment (6)

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Dynamic Power (6)

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HDM (6)

HVL (6)

Hardware Designs (6)

Hardware-Assisted Verification (6)

Hierarchical Data Model (6)

IC Design (6)

Implicit/Explicit (6)

June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

PCIe Gen 7 (6)

Phases (6)

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Semiconductor (6)

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Split Transactor (6)

Static Analyses (6)

Static RDC (6)

Stimulus Free Verification (6)

Tessent Test Solutions (6)

Transactors (6)

USB (6)

UVM Forum (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VA Live 2026 - Hudson (6)

VHDL Testbench (6)

Verification Cycles (6)

Virtual Prototyping (6)

Visualization (6)

YAML (6)

osmosis 2024 A&D (6)

Advance Your Verification Methodology (5)

Agile Development (5)

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Argument (5)

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BIST (5)

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CHERI (5)

CXL (5)

Checkpoint (5)

Class Library (5)

Co-Verification (5)

Constraint Solver (5)

Control Logic (5)

DAC 2024 (5)

DSP (5)

Data Encryption (5)

Debug Challenges (5)

December 2019 - Volume 15 Issue 3 (5)

Design Creation (5)

Design Cycle (5)

Design for Safety (5)

Domain Specific Architectures (5)

Driver Tracing (5)

Dual Top (5)

Error (5)

Exhaustive (5)

February 2019 - Volume 15 Issue 1 (5)

Formal Methods (5)

Formal Testbench (5)

Function (5)

HBM (5)

HBM4 (5)

Hardware Verification (5)

High-Speed (5)

IDE (5)

IP Blocks (5)

In-Circuit Emulation (5)

JEDEC (5)

LRM (5)

Low Latency (5)

Low Power Verification Forum (5)

MARLUG 2024 (5)

MARLUG 2025 (5)

March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

Memory-Mapped Registers (5)

Metastability Injection (5)

Model Context Protocol (5)

Multi-Language Environment (5)

NVM Express (5)

Namespaces (5)

Non-Pipelined (5)

Non-Reset (5)

PCIe Gen 8 (5)

Partitioning (5)

Processor Core Verification (5)

Quirky (5)

RTL Model (5)

Repository (5)

Reset Signal (5)

SFV (5)

SSD (5)

SVTB (5)

SVUnit (5)

Sequential Optimization (5)

Serial Interface (5)

Shift Left (5)

Simulink (5)

State-Based Model (5)

Stimulus Pattern (5)

Test Coverage (5)

Transaction-Based Acceleration (5)

UART (5)

UVC (5)

Unreachability (5)

VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

VA Live 2024 - Huntsville (5)

VA Live 2024 - Westford (5)

VA Live 2025 - Silicon Valley (5)

VA Live 2026 - El Segundo (5)

Verbose (5)

Verification Case Document (5)

Verification Success (5)

Virtual Methods (5)

X-Aware (5)

X-Mitigation (5)

5G (4)

AHB (4)

AMS Engines (4)

AMS Simulation (4)

Architectural Verification (4)

Batch and Debug (4)

Bi-Directional (4)

Bias (4)

Bit Width (4)

Boolean (4)

Boundary Elements (4)

Bounded Model Checking (4)

CDC Violations (4)

CPU Model (4)

Case Statements (4)

Class Variables (4)

Classifications (4)

Cone of Influence (4)

Coverage Achievement (4)

DVFS (4)

Data Processing (4)

Deprecated (4)

Design Analysis (4)

Design Specification (4)

Determinism (4)

Digital Domain (4)

DisplayPort (4)

Domain Configuration (4)

ECO (4)

ED-80 (4)

ENV Package (4)

Enumeration (4)

Equivalence Validation (4)

Equivalent RTL (4)

Fault Coverage (4)

Fault Detection (4)

Fault List (4)

Fibre Channel (4)

Formal Closure (4)

Formal Models (4)

HDMI (4)

Hybrid Virtual Platform (4)

ICE Mode (4)

IEEE (4)

Implementation Driven Formal (4)

Implementation Pattern (4)

In-Circuit Simulation (4)

In-System Test (4)

Initial States (4)

Instantiate (4)

LFM (4)

Language Constructs (4)

Large Language Models (4)

Mathworks (4)

Mitigation Architecture (4)

Monitor (4)

November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

Packet Transfer (4)

Parallel Compile (4)

Phase Objections (4)

Pipe Interface (4)

Plusargs (4)

Power Constraints (4)

Protocol Checkers (4)

Proxy Class (4)

QEMU (4)

QoR (4)

Questa Design Solutions (4)

RTL Verification (4)

RTL-Aware Design (4)

Race Conditions (4)

Reconfiguration (4)

Resource Utilization (4)

Retargeting Flow (4)

Risk Mitigation (4)

Semantics (4)

Sequential Logic (4)

Specification Pattern (4)

Static Timing (4)

Stream (4)

Structural Checks (4)

Subscriber (4)

Synchronizer (4)

Synergistic Verification (4)

Synthesizable (4)

Tcl/Tk (4)

Test Ranking (4)

Time Cone (4)

Tool Optimization (4)

Toolkit (4)

Top Down (4)

Trust Verification (4)

UCIS (4)

UEC (4)

UPF 3.0 (4)

UPF 4.0 (4)

UVM 1.1d (4)

UVM 1.2 (4)

UVM Monitor (4)

Unidirectional (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

VA Live 2026 - Silicon Valley (4)

VPM (4)

Vectors (4)

Verification Blueprint (4)

Virtual Sequencers (4)

Wave Window (4)

$display (3)

1.2 (3)

AMS Verification (3)

APB3 (3)

Abstract Class (3)

Abstract-Concrete (3)

Access Path (3)

Affect Probability (3)

Airborne Electronic Hardware (3)

Analysis Components (3)

Base Test (3)

BiQuad (3)

Bidirectional Protocols (3)

Block Diagram (3)

Build Process (3)

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CDC Signals (3)

CSI-2 (3)

Cause-Effect (3)

Certification (3)

Clock Definitions (3)

Clock Detection (3)

Clocking (3)

Code Quality (3)

Command Line Processor (3)

Connect Phase (3)

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Coroutines (3)

Cover Method (3)

Coverage Data (3)

Coverage Exclusion (3)

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Critical Storage (3)

Cross-Domain (3)

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Cutpoint (3)

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Design Under Test (3)

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ESL (3)

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Golden Model (3)

HLV (3)

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Horizontal Reuse (3)

Illegal Bins (3)

Integrity Challenges (3)

Intelligent Integration (3)

JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

Lane Margining (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

Loop Statements (3)

MC2 (3)

MUX (3)

Mailboxes (3)

Mathematical Analysis (3)

Memory Debug (3)

Method (3)

NRRs (3)

NoC (3)

OSVVM (3)

Observability (3)

Observer (3)

Open Architecture (3)

Operating State (3)

PCI-SIG (3)

Package Organization (3)

Parallel Computing (3)

Phase-Level (3)

Polymorphic Behavior (3)

Power Architecture (3)

Power Consumption (3)

Power Gating (3)

Protocol Layers (3)

QFL (3)

Qrun (3)

Quality Assurance (3)

RISC-V Verification Interface (3)

RTL Emulation (3)

Radiation Mitigation (3)

Re-targeting (3)

Real Number Modeling (3)

Regime (3)

Retimers (3)

Routines (3)

SDC (3)

SDC Verification (3)

Safety Assurance (3)

Scripting (3)

Security Coverage (3)

Security Vulnerabilities (3)

Semaphores (3)

Sign-Off Methodology (3)

Signal Property (3)

Signal-Level (3)

Single Step Debug (3)

Singleton (3)

Slave Agent (3)

Soft Reset (3)

Source Code Management (3)

Specification Driven Formal (3)

Spiral Refinement (3)

State Transition (3)

Static Lists (3)

Static Properties (3)

Subsystem (3)

System Confidence (3)

System Verification (3)

TBX (3)

TDISP (3)

Task Call (3)

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November 2022

Episode 2: The Current Trends in FPGA Verification
Planning, Measurement and Analysis Nov 02, 2022 Harry Foster link
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai Webinar
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai pdf

October 2022

Part 3: FPGA Verification Effort Trends
Planning, Measurement and Analysis Oct 30, 2022 Harry Foster link
ISO 26262…the Tale of Transient and Permanent Faults
Functional Safety Oct 27, 2022 Jacob Wiltgen link
Episode 1: The Growing Complexity in Field Programmable Gate Arrays (FPGA)
Planning, Measurement and Analysis Oct 26, 2022 Harry Foster link
CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma pdf
CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma Webinar
Part 2: FPGA Verification Effectiveness Trends
Planning, Measurement and Analysis Oct 24, 2022 Harry Foster link
Industry Data and Surveys
Planning, Measurement and Analysis Oct 24, 2022 Harry Foster Track
Formal and the Next Normal
Formal Verification Oct 19, 2022 Joe Hupcey Webinar
Dig a Pool of Specialized SystemVerilog Classes
SystemVerilog Oct 17, 2022 Chris Spear link
Part 1: FPGA Design Trends
Planning, Measurement and Analysis Oct 16, 2022 Harry Foster link
Prologue: The 2022 Wilson Research Group Functional Verification Study
Planning, Measurement and Analysis Oct 10, 2022 Harry Foster link
UVM Testbench Debug – A Day At The Beach – Right?
Debug Oct 04, 2022 Rich Edelman link

September 2022

Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs
Formal Verification Sep 30, 2022 Martin Rowe Webinar
SystemVerilog: Implicit handles
SystemVerilog Sep 06, 2022 Chris Spear link

August 2022

SystemVerilog: Class Member Visibility
SystemVerilog Aug 29, 2022 Chris Spear link
UVM Framework Release 2022.3
UVM Framework Aug 15, 2022 Bob Oden tar

July 2022

Finding Data
Debug Jul 28, 2022 Rich Edelman link
How to Use Checklists for DO-254 Verification
Functional Safety Jul 07, 2022 Tammy Reeve - Patmos Engineering Services link
Back to the Future with Formal Property Checking
Formal Verification Jul 05, 2022 Harry Foster Article
The Democratization of Digital Methodologies for AMS Verification
Analog Mixed-Signal Jul 05, 2022 Sumit Vishwakarma Article
Getting to Know Visualizer - Part II
Debug Jul 05, 2022 Rich Edelman Article
Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Verification IP Jul 05, 2022 Himani Kaushik - Siemens Eda Article

New White Paper!

2026 Functional Verification Study: Executive Findings

New White Paper!

Five Signals from the 2026 Functional Verification Study

New White Paper!

AI in Functional Verification: What the 2026 Industry Data Reveals

New White Paper!

DFT's Expanding Role in Software-Driven Silicon: From Structural Test Closure to System-Assurance Evidence

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