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Show Less

July 2022

The Path to a Safety Mechanism on an Unsafe PCIe® Sub-Module
Functional Safety Jul 05, 2022 Avnita Pal - Silicon Interfaces Article

June 2022

Questa Lint vs Formal AutoCheck
Questa Design Solutions Jun 15, 2022 Kevin Campbell Webinar
Questa Lint vs Formal AutoCheck
Questa Design Solutions Jun 15, 2022 Kevin Campbell pdf
The Three Pillars of Intent-Focused Insight
Planning, Measurement and Analysis Jun 08, 2022 Harry Foster Webinar

May 2022

Advanced Debug Techniques
Debug May 23, 2022 Rich Edelman Track
UVM Connect
UVMC May 23, 2022 Adam Erickson Track
SystemVerilog OOP for UVM Verification
SystemVerilog May 23, 2022 Dave Rich Track
Advanced UVM
UVM - Universal Verification Methodology May 23, 2022 Tom Fitzpatrick Track
Verilog & VHDL Debug & Weeding
Debug May 18, 2022 Rich Edelman link
Aerospace and Defense Verification Tech Day
Functional Safety May 11, 2022 Joe Hupcey Track
Siemens and the US Government - Mitigating Microelectronics Development Challenges
Functional Safety May 10, 2022 Rich Powlowsky Webinar
Bringing Model-based Systems Engineering to IC and FPGA Design
FPGA Verification May 10, 2022 Ray Salemi Webinar
From Model to Implementation with High-Level Synthesis
High-Level Synthesis May 10, 2022 Russell Klein Webinar
Accelerate Learning Curves and Achieve Program Goals Efficiently
Questa Design Solutions May 10, 2022 Chris Giles Webinar
Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
UVM Framework May 10, 2022 Bob Oden Webinar
How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification
Formal Verification May 10, 2022 Joe Hupcey Webinar
Accelerate Development Using Advanced Debugging Approaches
Debug May 10, 2022 Rich Edelman Webinar
Collaborative Verification Management & Coverage Analysis
Verification Management May 10, 2022 Darron May Webinar
Securing the Electronics Development Chain with IC Integrity Solutions
Formal Verification May 10, 2022 John Hallman Webinar
System Level SoC Verification and Validation Using Emulation and Prototype Platforms
Acceleration May 10, 2022 Vijay Chobisa Webinar
Trust but Verify Your IP with Solido Crosscheck
Analog Mixed-Signal May 10, 2022 Felipe Schneider Webinar

March 2022

System Verification with MatchLib
High-Level Synthesis Mar 31, 2022 Russell Klein mp4
System Verification with MatchLib
High-Level Synthesis Mar 31, 2022 pdf
The “Formal 101” Series: Learn Formal the Easy Way
Formal Verification Mar 29, 2022 Joe Hupcey Track
The Best Verification Strategy You’ve Never Heard Of
Planning, Measurement and Analysis Mar 28, 2022 pdf

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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