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January 2025

Unlocking the Power of QuestaSim and Visualizer Integration
Simulation Jan 15, 2025 Justin Royse pdf
Introduction to Functional Verification
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Understanding the Two Main Testing Approaches
UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster pdf
What is a Reusable Testbench?
UVM - Universal Verification Methodology Jan 10, 2025 Tom Fitzpatrick pdf
How Can I Reuse Testbench Components?
UVM - Universal Verification Methodology Jan 10, 2025 Tom Fitzpatrick pdf
UVM Test Flow
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Creating a Test Plan
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Test Plan Fields
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
SystemVerilog Data Types
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Multidimensional Arrays
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Built-In Unpacked Arrays
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Procedural Programming Statements
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Introduction to Functional Coverage
UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster pdf
SystemVerilog Coverage Constructs
UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster pdf
Reusable Coverage, Reporting, and Options
UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster pdf
Sampling and Using Coverage
UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster pdf
Introduction to Constrained Random Stimulus
UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich pdf
Verilog Expression Impact on Constraints
UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich pdf
Issues Contributing to Randomization Failures
UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich pdf
Random Stimulus Probabilities and Statistics
UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich pdf
Random Variable and Constraint Features
UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster pdf
Connecting the DUT and Testbench
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Interface Ports, Timing, and Direction
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Implementing Protocol Signaling
UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf
Timing and Execution Semantics
UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster pdf

FPGA Webinar

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Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

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Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

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Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

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January 2025

Unlocking the Power of QuestaSim and Visualizer Integration

Introduction to Functional Verification

Understanding the Two Main Testing Approaches

What is a Reusable Testbench?

How Can I Reuse Testbench Components?

UVM Test Flow

Creating a Test Plan

Test Plan Fields

SystemVerilog Data Types

Multidimensional Arrays

Built-In Unpacked Arrays

Procedural Programming Statements

Introduction to Functional Coverage

SystemVerilog Coverage Constructs

Reusable Coverage, Reporting, and Options

Sampling and Using Coverage

Introduction to Constrained Random Stimulus

Verilog Expression Impact on Constraints

Issues Contributing to Randomization Failures

Random Stimulus Probabilities and Statistics

Random Variable and Constraint Features

Connecting the DUT and Testbench

Interface Ports, Timing, and Direction

Implementing Protocol Signaling

Timing and Execution Semantics