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February 2019

The Big Brain Theory: Visualizing SoC Design and Verification Data
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Efficient Modeling Styles and Methodology for Gate-Level Design Verification
Questa Design Solutions Feb 28, 2019 Rohit Jain pdf
UVM IEEE Shiny Object
UVM - Universal Verification Methodology Feb 28, 2019 Rich Edelman pdf
The Missing Link: The Testbench to DUT Connection
SystemVerilog Feb 28, 2019 Dave Rich pdf
Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Clock-Domain Crossing Feb 28, 2019 Ping Yeung pdf
Clock-Domain Crossing (CDC) Challenges in Latch Based Designs
Clock-Domain Crossing Feb 28, 2019 Kurt Takara pdf
Low Power Apps: Shaping the Future of Low Power Verification
Low Power Feb 28, 2019 pdf
Formal Techniques for Optimizing ISO 26262 Fault Analysis
Functional Safety Feb 28, 2019 Doug Smith pdf
Using Strong Types in SystemVerilog Design and Verification Environments
SystemVerilog Feb 28, 2019 Dave Rich pdf
Choosing a Format for the Portable Stimulus Specification
Portable Stimulus Feb 22, 2019 Matthew Ballance pdf

January 2019

Accelerating Verification through Verification IP, Configurator and UVM Framework
Verification IP Jan 24, 2019 Sharath Kannareddy pdf
Making Verification Fun Again
UVM Framework Jan 24, 2019 Jonathan Craft pdf
Verification Acceleration for FPGA Designs with Matlab
Acceleration Jan 24, 2019 Jerry Grula - Siemens Eda pdf
Welcome & Overview
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf
ASIC & FPGA SoC Functional Verification Trends
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf

December 2018

Effective Elements List and Transitive Natures of UPF Commands
Low Power Dec 21, 2018 Progyna Khondkar pdf
C Stimulus Package (.tgz)
UVM - Universal Verification Methodology Dec 04, 2018 Verification Methodology Team tar

October 2018

Planning for DO-254
Functional Safety Oct 10, 2018 Byron Brinson pdf
DO-254 in Simple Terms
Functional Safety Oct 04, 2018 Byron Brinson pdf

September 2018

UVM 1800.2 and the New & Improved Cookbook
UVM - Universal Verification Methodology Sep 27, 2018 pdf
A Fresh Look at Creating a UVM Environment - UVM Framework
UVM Framework Sep 27, 2018 pdf
A Fresh Look at Creating a UVM Environment - All Slides
UVM - Universal Verification Methodology Sep 27, 2018 zip
A Fresh Look at Creating a UVM Environment - Introduction
UVM - Universal Verification Methodology Sep 27, 2018 pdf
Vista Virtual Prototyping
Functional Safety Sep 27, 2018 pdf
Visualizer Debug Introduction
Debug Sep 27, 2018 pdf

FPGA Webinar

Wednesday, Jul 22nd-8:00 AM PDT

Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

Browse all Resources in Siemens Verification Academy

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