Browse all Papers in Siemens Verification Academy
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March 2020
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If You Don’t Know, Now You Know: Terminal Boundary Dictates Power Aware Macros
Low Power Mar 14, 2020 Paper
August 2019
July 2019
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Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps
Low Power Jul 07, 2019 Paper
June 2019
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Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify Use Models
Coverage Jun 15, 2019 Paper -
A Specification-Driven Methodology for the Design and Verification of RDC Logic
Reset-Domain Crossing Jun 11, 2019 Paper
May 2019
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Debugging Functional Coverage Models: Get the Most Out of Your Cover Crosses
Coverage May 13, 2019 Paper
March 2019
February 2019
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Using Strong Types in SystemVerilog Design and Verification Environments
SystemVerilog Feb 28, 2019 Paper -
Efficient Modeling Styles and Methodology for Gate-Level Design Verification
Questa Design Solutions Feb 28, 2019 Paper -
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Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Clock-Domain Crossing Feb 28, 2019 Paper -
Clock-Domain Crossing (CDC) Challenges in Latch-Based Designs
Clock-Domain Crossing Feb 28, 2019 Paper
December 2018
August 2018
February 2018
November 2017
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Go Figure – UVM Configure: the Good, the Bad, the Debug
UVM - Universal Verification Methodology Nov 10, 2017 Paper
October 2017
March 2017
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Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Low Power Mar 20, 2017 Paper -
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
Verification Management Mar 13, 2017 Paper
