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Show Less

December 2016

How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration
Formal Verification Dec 05, 2016 Mark Eslinger Webinar

November 2016

Industry Trends in Today’s Functional Verification Landscape
Planning, Measurement and Analysis Nov 11, 2016 Harry Foster Webinar
Enterprise Debug for Formal
Formal Verification Nov 11, 2016 Joe Hupcey Webinar
Enterprise Debug for Simulation
Debug Nov 11, 2016 Moses Satyasekaran Webinar
INs and OUTs of CAN Verification—A Comprehensive UVM-based Solution
Standards Nov 10, 2016 Verification Horizons Article
USB Type-C Verification: Challenges and Solution
Simulation Nov 10, 2016 Verification Horizons Article
How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology
Standards Nov 10, 2016 Verification Horizons Article
Power Aware Libraries: Standardization and Requirements for Questa Power Aware
Low Power Nov 07, 2016 Progyna Khondkar Article
Improving Performance and Verification of a System Through an Intelligent Testbench
Simulation Nov 07, 2016 Umesh Patel, Dhaval Shah - Arastu Systems Pvt. Ltd. Article

October 2016

Functional Verification Study - 2016
Planning, Measurement and Analysis Oct 14, 2016 Harry Foster Session

August 2016

Extending a Traditional VIP to Solve PHY Verification Challenges
Verification IP Aug 26, 2016 pdf
Beyond UVM Registers - Better, Faster, Smarter
UVM - Universal Verification Methodology Aug 25, 2016 Rich Edelman Paper
Beyond UVM Registers - Better, Faster, Smarter
UVM - Universal Verification Methodology Aug 25, 2016 Rich Edelman pdf
Total Recall - What to Look for in a Memory Model Library
Verification IP Aug 24, 2016 pdf
Three Steps to Unified SoC Design and Verification
Standards Aug 19, 2016 Mark Peryer Article
Staying Competitive with Advanced FPGA Verification
FPGA Verification Aug 10, 2016 Bryan Ramirez Webinar

June 2016

Trends in Functional Verification
Planning, Measurement and Analysis Jun 20, 2016 Harry Foster pdf
Debug Data API Update
Debug Jun 20, 2016 Rich Edelman pdf
Get Ready for Portable Stimulus
Portable Stimulus Jun 20, 2016 Tom Fitzpatrick pdf
Verification IP and Memory Models Improve Productivity and Reduce Risk
Verification IP Jun 20, 2016 Mark Olen pdf
Back to the Stone Ages for Advanced Verification
Planning, Measurement and Analysis Jun 20, 2016 Neil Johnson pdf
Marking Milestones: In Life and in Technology
Simulation Jun 14, 2016 Verification Horizons Article
SW-HW Pipe
Planning, Measurement and Analysis Jun 10, 2016 Harry Foster pdf
How Formal Techniques Can Keep Hackers from Driving You into a Ditch
Formal Verification Jun 01, 2016 Joe Hupcey Article
Simplifying HDCP Verification Using Questa Verification IP
Verification IP Jun 01, 2016 Raman Jain, Priya Minocha - Siemens Eda Article

DAC 2025

Exhibitor Forum: Smart Verification for Modern Complexity

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Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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December 2016

How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration

November 2016

Industry Trends in Today’s Functional Verification Landscape

Enterprise Debug for Formal

Enterprise Debug for Simulation

INs and OUTs of CAN Verification—A Comprehensive UVM-based Solution

USB Type-C Verification: Challenges and Solution

How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology

Power Aware Libraries: Standardization and Requirements for Questa Power Aware

Improving Performance and Verification of a System Through an Intelligent Testbench

October 2016

Functional Verification Study - 2016

August 2016

Extending a Traditional VIP to Solve PHY Verification Challenges

Beyond UVM Registers - Better, Faster, Smarter

Beyond UVM Registers - Better, Faster, Smarter

Total Recall - What to Look for in a Memory Model Library

Three Steps to Unified SoC Design and Verification

Staying Competitive with Advanced FPGA Verification

June 2016

Trends in Functional Verification

Debug Data API Update

Get Ready for Portable Stimulus

Verification IP and Memory Models Improve Productivity and Reduce Risk

Back to the Stone Ages for Advanced Verification

Marking Milestones: In Life and in Technology

SW-HW Pipe

How Formal Techniques Can Keep Hackers from Driving You into a Ditch

Simplifying HDCP Verification Using Questa Verification IP