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March 2017 - Volume 13 Issue 1 (3)

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December 2019 - Volume 15 Issue 3 (2)

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Formal Verification Mar 01, 2020 Tomáš Vaňák - Codasip Article
An Open Data Management Tool for Design and Verification
Verification Management Mar 01, 2020 Vishal Patel, Manoj Pandey - Arastu Systems Article

January 2020

Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
Standards Jan 07, 2020 Matthew Ballance Article
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Standards Jan 07, 2020 Joe Hupcey Article
Low Power Coverage: The Missing Piece in Dynamic Simulation
Simulation Jan 07, 2020 Progyna Khondkar Article
Low Power Apps: Shaping the Future of Low Power Verification
Standards Jan 07, 2020 Verification News Article
Managing and Automating HW/SW Tests from IP to SoC
Simulation Jan 07, 2020 Matthew Ballance Article
Reusable UPF: Transitioning from RTL to Gate Level Verification
Standards Jan 07, 2020 Verification News Article
Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy
Standards Jan 07, 2020 Matthew Ballance Article
Results Checking Strategies with Portable Stimulus
Standards Jan 07, 2020 Matthew Ballance Article
Coverage Driven Verification of NVMe Using Questa VIP
Simulation Jan 07, 2020 Verification News Article
Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task
Functional Safety Jan 07, 2020 Charles Battikha Article

December 2019

Achieving Functional Safety for Autonomous Vehicle SoC Designs
Functional Safety Dec 06, 2019 Jake Wiltgen Article
Exercising State Machines with Command Sequences
Portable Stimulus Dec 03, 2019 Matthew Ballance Article
Designing A Portable Stimulus Reuse Strategy
Portable Stimulus Dec 03, 2019 Matthew Ballance Article

November 2019

UVMC 2.3.2 Library
UVMC Nov 15, 2019 html

October 2019

Questa PropCheck GUI - Waveform View
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Why RDC Verification is an Emerging Requirement
Questa Design Solutions Oct 01, 2019 Kurt Takara Webinar
Why RDC Verification is an Emerging Requirement
Questa Design Solutions Oct 01, 2019 Kurt Takara pdf

September 2019

Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden Session
Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden pdf
Code Generation Guidelines
UVM Framework Sep 09, 2019 Bob Oden Session
Code Generation Guidelines
UVM Framework Sep 09, 2019 Jonathan Craft pdf

August 2019

Machine-Learning-Assisted Agile VLSI Design for Machine Learning
Machine Learning Aug 31, 2019 Brucek Khailany link
Coverage Driven Verification of NVMe Using Questa VIP
Verification IP Aug 21, 2019 pdf

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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