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September 2021 - Volume 17 Issue 2 (7)

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June 2018 - Volume 14 Issue 2 (6)

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November 2020 - Volume 16 Issue 3 (5)

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December 2022 - Volume 18 Issue 3 (4)

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February 2013 - Volume 9 Issue 1 (4)

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June 2019 - Volume 15 Issue 2 (4)

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December 2019 - Volume 15 Issue 3 (3)

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February 2019 - Volume 15 Issue 1 (3)

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January 2017

Seven Separate Sequence Styles Speed Stimulus Scenarios
Standards Jan 03, 2017 Mark Peryer Article
The Need For Speed: Understanding Design Factors That Make Multi-Core Parallel Simulations Efficient
Simulation Jan 03, 2017 Verification Methodology Team Article
Traffic Profiling and Performance Instrumentation For On-Chip Interconnects
Standards Jan 03, 2017 Mark Peryer Article
UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process
Standards Jan 03, 2017 Verification Methodology Team Article
Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program
Standards Jan 03, 2017 Mike Horn Article
Equivalence Validation of Analog Behavioral Models
Analog Mixed-Signal Jan 03, 2017 Verification Methodology Team Article
Interpreting UPF For A Mixed-Signal Design Under Test
Standards Jan 03, 2017 Verification Methodology Team Article
Using Test-IP Based Verification Techniques in a UVM Environment
Standards Jan 03, 2017 Verification Methodology Team Article
Is Your Power Aware Design Really X-Aware?
Simulation Jan 03, 2017 Verification Methodology Team Article
Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification
Standards Jan 03, 2017 Verification Methodology Team Article
So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
Simulation Jan 03, 2017 Andreas Meyer Article
Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?
Verification Management Jan 03, 2017 Darron May Article
Bringing Regression Systems into the 21st Century
Verification Management Jan 03, 2017 Thom Ellis Article

December 2016

Jenkins Tutorial - Setup, Install, Configuration
Planning, Measurement and Analysis Dec 23, 2016 Darron May pdf
JUnit Plugin (required)
Planning, Measurement and Analysis Dec 23, 2016 link
Questa VRM
Planning, Measurement and Analysis Dec 23, 2016 Darron May link
Jenkins Release
Planning, Measurement and Analysis Dec 23, 2016 link
Dashboard View (optional)
Planning, Measurement and Analysis Dec 23, 2016 link
Best Practices for FPGA and ASIC Development
Simulation Dec 21, 2016 Verification Horizons Article
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Dec 19, 2016 Saumya Agrawal Paper
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Dec 19, 2016 Saumya Agrawal pdf
How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration
Formal Verification Dec 05, 2016 Mark Eslinger Webinar

November 2016

Improving Performance and Verification of a System Through an Intelligent Testbench
Standards Nov 17, 2016 Verification Horizons Article
Questa Verification IP Configurator
Verification IP Nov 14, 2016 Dave Aerne Webinar
Questa Verification IP PCIe®
Verification IP Nov 14, 2016 Akshay Sarup Webinar

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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