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December 2022 - Volume 18 Issue 3 (4)

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February 2019 - Volume 15 Issue 1 (3)

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March 2017 - Volume 13 Issue 1 (3)

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November 2018 - Volume 14 Issue 3 (3)

October 2012 - Volume 8 Issue 3 (3)

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December 2019 - Volume 15 Issue 3 (2)

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July 2023 - Volume 19 Issue 2 (2)

Latch-Based Designs (2)

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March 2015 - Volume 11 Issue 1 (2)

Memory Debug (2)

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December 2017 - Volume 13 Issue 3 (1)

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January 2022

Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee pdf
Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee Webinar
Odds and Ends
Python Jan 14, 2022 Ray Salemi link

December 2021

Logging in PYUVM
Python Dec 14, 2021 Ray Salemi link
Courtines and COCOTB Testbench Code
Python Dec 14, 2021 Ray Salemi link

November 2021

The UVM Factory
Python Nov 17, 2021 Ray Salemi link

October 2021

The Configuration Database in PYUVM
Python Oct 27, 2021 Ray Salemi link
TLM 1.0 in pyuvm
Python Oct 01, 2021 Ray Salemi link

September 2021

Questa Lint - Find and Fix RTL Issues
Questa Design Solutions Sep 14, 2021 Tom Carlstedt-Duke Demo
Python and the UVM
Python Sep 09, 2021 Ray Salemi link
What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Formal Verification Sep 01, 2021 Tom Fitzpatrick Article
Hardware-Assisted Verification Through the Years
Acceleration Sep 01, 2021 Jean-Marie Brunet Article
"Hug the Debug" – Before It’s Too Late
Debug Sep 01, 2021 Sumit Vishwakarma Article
Questa Visualizer Adds Coverage Analysis to the Platform
Debug Sep 01, 2021 Yara Esam - Siemens Eda Article
Verifying a DDR5 Memory Subsystem
Verification IP Sep 01, 2021 Kamlesh Mulchandani Article
Expediting Simulation Turn-around Time with Incremental Build Flow
Simulation Sep 01, 2021 Neil Johnson Article
Standards Participation at Siemens EDA
Standards Sep 01, 2021 Dave Rich Article

August 2021

UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level
UVM Framework Aug 05, 2021 Pedram Riahi - Raytheon Conference

July 2021

Managing Requirements in a Functional Safety Environment
Functional Safety Jul 29, 2021 Thorsten Stahlberg - Siemens Eda Webinar
Digital Functional Verification for Safety-Critical Automotive Applications
Functional Safety Jul 29, 2021 Michael Bierl - Siemens Eda Webinar
CDC Verification: Beyond Structural Analysis
Clock-Domain Crossing Jul 29, 2021 Mark Handover Webinar
UVM Framework Release 2021.3
UVM Framework Jul 13, 2021 Bob Oden tar

May 2021

Introducing Transactions | Japanese
UVM - Universal Verification Methodology May 28, 2021 Tom Fitzpatrick pdf
How TLM Works
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
The Proper Care and Feeding of Sequences
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

UALink VIP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

osmosis Europe 2025

Thursday, October 16th, 2025 - Munich, DE

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

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