Verification Horizons Articles:
by Tom Fitzpatrick, Siemens EDA
Welcome to this very special edition of Verification Horizons! As many of you are aware, Mentor Graphics was acquired by Siemens a few years ago, and things were finally completed earlier this year. That means that we are now Siemens EDA, and I am excited to share with you – for the first time in Verification Horizons – some of what you can expect to see as a result of this process. I recently spoke with Ravi Subramanian, our Senior VP of IC Verification Solutions, to get his take on all the great things we’ve been able to accomplish since officially becoming Siemens EDA. He told me that the Siemens acquisition a few years ago gave us a unique opportunity to invest in our traditional product portfolio and to build solutions combining the best of our Mentor heritage with the breadth of Product Lifecycle and other key technologies from Siemens. Combined with the resources to acquire complementary tools, technologies, and solutions, we are now uniquely positioned as Siemens EDA to provide more value beyond our traditional EDA competitors and help our customers verify their systems and chips well into the future.
by Tom Fitzpatrick, Harry Foster and Dominik Strasser, Siemens EDA
Preface: in May 2021 Siemens EDA acquired OneSpin Solutions, combining Siemens' Questa Formal products and expertise (with roots and team members from 0-In) with OneSpin’s “apps first” approach to key growth markets including Trust&Security, Safety, RISC-V, and FPGAs. The combination adds to a cohesive Siemens EDA verification solution spanning simulation, formal, emulation, and prototyping. To find out what this means for the future of formal technology – and how end-users will benefit -- I’ve interviewed Formal experts Harry Foster (of the Wilson Survey fame, DAC 2021 General Chair chairman, among other roles), and Dominik Strasser (a co-founder of OneSpin; now in Siemens R&D).
by Ray Salemi, Siemens EDA and Lisa Murphy, Siemens DISW
In October of 2020, the Air Force challenged Aerospace and Defense industry to adopt the suggestions presented in the 2018 Digital Engineering Strategy. The document, named "There is No Spoon: The New Digital Acquisition Reality”, warns that aircraft design and deployment must embrace “the digital trinity” of Digital Engineering and Management, Agile Software Development, and Open Architecture to create an improved development system that enables the United States and its allies to compete with the superior number of Chinese Aerospace and Defense development and establish a robust and secure supply chain.
by Ann Keffer, Siemens EDA
Developers of ICs, systems, and even vehicles are seeing some pretty significant shifts in the automotive industry. Recent estimates forecast that 50% of a vehicle’s Bill of Materials (BOM) will be electronics and electronic systems by the year 2030. Smart mobility is the root cause as the market demands features such as lane keep, adaptive cruise control, and emergency brake assist to name a few. Longer term, the market will demand the feature set required to support level 4 (eyes off) and level 5 (mind off) autonomous driving.
byTammy Reeve, Patmos Engineering Services, Jacob Wiltgen, Byron Brinson and David Aerne, Siemens EDA
The adoption of tools into safety-critical workflows is often challenging as these new technologies must demonstrate sufficient safeness to use before being deployed in production environments. The demand for High-Level Synthesis capabilities within DO-254 projects is growing and this paper describes the requirements and considerations to successfully use High-Level Synthesis within a DO-254 workflow.
by Jean-Marie Brunet, Siemens EDA and Lauro Rizzatti, Verification Consultant and Industry Expert
A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. When combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in hardware. The focus on tools and delivering a tightly woven integration between complementary tools is a strategic focus at Siemens EDA. This is illustrated by the large number of tools in the Siemens Xcelerator portfolio.
by Jean-Marie Brunet, Siemens EDA
Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof. According to market research International Business Strategies (IBS), the total cost of designing a state-of-the-art system on chip (SoC) at the 5nm process technology node exceeds half a billion dollars. Of all the stages that make up the entire design creation and verification flow, two account for more than 60% of the total cost.
by Stephen Bailey and Antonio Costa, Siemens EDA
In a 2010 inaugural issue of the report from the UK High Performance Computing Special Interest Group (HPC-SIG), the following statement resonated with a large number of companies and research institutions that were using HPC technology. "Over the past decade there has been a revolution in High Performance Computing spearheaded by a movement away from using expensive traditional proprietary supercomputers to systems based on relatively inexpensive commodity off-the-shelf systems." [1]
by Sumit Vishwakarma, Siemens EDA
Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by the global chip shortage, especially in the automotive industry. Manufacturing a robust chip is a long iterative process which may require many re-spins. Shift-left refers to finding and fixing bugs early in the development cycle rather than catching them during implementation where they are up to 100 times more expensive to fix.
by Yara Esam, Siemens EDA
Questa Visualizer Debug is our high performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs. Visualizer recently introduced new functionality for coverage support giving the user many ways to analyze and improve coverage closure with ease. Starting with Coverage gives you another way to diagnose problems, Visualizer provides great improvement to the coverage data representation, taking advantage of its existing rich visualization capabilities.
by Raman Jain and Kamlesh Mulchandani, Siemens EDA
The latest technologies and applications often demand more speed and performance. With the advancement in technologies such as multi-core CPUs and GPUs, the need for faster data processing is becoming a bottleneck for system performance. Applications such as Machine Learning and Data Centers rely upon high performance and lower latency. These applications need a memory that can offer high speed, better performance, high density, lower latency, and data integrity. Looking at the memory trends: DDR4 came out in 2014, starting out at 1600 MHz speeds which eventually reached 3200 MHz at the very high end.
by Neil Johnson, Siemens EDA
Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use to constantly validate progress. Whether the result is a failed compile, passing simulation or anything in between, the sooner you get that result, the sooner you get to the next step and closer you get to your ultimate objective: passing silicon.
by Dave Rich, Siemens EDA
All of us are involved with standards every day whether we realize it or not. From the day we are born, we interact with standards. In the US, a baby receives a standardized health assessment score called Apgar after 1 minute. You are weighed and measured to standards. You wear clothes sized to standards. Eventually, you learn to read and write according to some culturally accepted standards.
