Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP
In this webinar, you will be introduced to the UALink protocol, focusing on its architecture and key features that enable scalable AI systems. We will then dive into the essential capabilities of Siemens Avery UALink Verification IP, designed to ensure complete and efficient verification of complex UALink-based accelerator designs.
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Session Registration
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Session Overview
The significant growth of data-intensive workloads in artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) requires high levels of computational power and efficient data movement.
Traditional system architectures and general-purpose interconnects are finding it challenging to keep pace with the large data flows and low-latency requirements of large-scale AI models and distributed accelerator systems. This creates an important need for specialized, high-bandwidth, and low-latency interconnects to enable seamless communication between multiple accelerators (GPUs, NPUs, etc.) and memory.
Ultra Accelerator Link (UALink) is emerging as a key open industry standard addressing these challenges. Specifically designed for accelerator-to-accelerator and accelerator-to-memory communication, UALink provides very high bandwidth, very low latency, and advanced scalability features essential for building next-generation AI superclusters and highly distributed computing environments. It aims to significantly enhance how AI accelerators communicate, enabling more efficient training of large models and faster inference.
Attendees of this webinar will be introduced to the UALink protocol, focusing on its architecture and key features that enable scalable AI systems. We will then dive into the essential capabilities of Siemens Avery UALink Verification IP, designed to ensure complete and efficient verification of complex UALink-based accelerator designs.
What You Will Learn
- UALink Overview: Get acquainted with the fundamental concepts, architecture, and potential applications of Ultra Accelerator Link (UALink) in AI and HPC.
- Future of UALink: Explore upcoming advancements, roadmaps, and their impact on next-generation AI hardware development.
- Siemens Avery UALink Verification IP: Dive into the unique features and potential benefits of Siemens Avery's UALink Verification IP for your projects.
- Technical Demonstration: Witness a practical demonstration of Siemens Avery UALink Verification IP.
Who Should Attend
- Design Verification Engineers and Managers
- Architects working on or planning AI accelerator
- High-performance computing
- UALink-based system design projects
Products Covered
- Avery UALink VIP
