Questa One Avery VIP: Accelerated Confidence in Complex Protocol Verification

In today’s rapidly advancing digital landscape, the role of functional verification has never been more critical. As systems become increasingly complex, ensuring their reliability and performance poses significant challenges for both design and verification engineers. The stakes are high; verification failures can lead to costly recalls, safety risks, and damage to brand reputation. The latest Wilson Research numbers show the amount of right-first-time silicon projects falling to 14% — its lowest level since the study began over 20 years ago — and 75% of ASIC projects are behind schedule. In response to these challenges, the industry is on the brink of a revolutionary shift driven by artificial intelligence (AI).

Considering these newly available AI capabilities, Siemens EDA is introducing new innovations and an approach that will transform established norms and break free of constraints that have become entrenched in the industry over the last three decades. We are enabling organizations to enhance accuracy, reduce time-to-market, and improve overall productivity. By leveraging data-driven approaches and machine learning (ML) algorithms, verification teams can gain insights previously unattainable and streamline workflows that have historically been time-consuming and error-prone.

These innovations are part of the Siemens Questa™ One Smart Verification solution, and Questa One Avery Verification IP (or Questa One Avery VIP) is a key part of this customer-centric offering designed to enable faster engines, faster engineers, and fewer workloads — the ultimate productivity.

Siemens Questa One Avery Verification IP solutions are built upon the foundation of Siemens’ indus­try-leading Questa One Avery VIP architecture, adding significant features and integrations that meet the challenges customers face today and tomorrow. These new capabilities will assist users in several ways: understanding how to use and how to integrate increasingly complex off-chip and 3D IC chip-to-chip interfaces and memory protocols; accelerating debug­ging activity across those connections with a suitable level of abstraction, building coverage-driven verifica­tion flows that leverage established protocol expertise to accelerate tape out, and enabling customers to focus precious resources on their own value-add by buying rather than building standard interface verification components.

As we explore the potential of Questa One Avery VIP to improve productivity, we will delve into the specific challenges the industry faces, showcase innovative solutions being developed, and highlight the value experienced by early adopters who have embraced these cutting-edge technologies. This transformative journey promises not only to enhance productivity but also to set the foundation for greater innovations in the future of functional verification.