Transaction-Level Friending: Connecting TLM Models in SystemC and SystemVerilog

A 2010 Wilson Research Group independent study of trends in functional verification confirmed that usage of SystemVerilog, SystemC, C, and C++ was growing, as was deployment of the Universal Verification Methodology (UVM), a SystemVerilog library of testbench building blocks and best practices.²

Each of the language and library standards used by the verification community possesses strengths suited to its intended purpose:

• C and C++ for software development and untimed modeling^3,4
• SystemC for high-speed architectural modeling of hardware and early collaboration with software teams⁵
• TLM 2.0 for interoperable, approximately timed (AT) and loosely timed (LT) transaction-level communication between independently design models⁵
• SystemVerilog for RTL and gate-level simulation, behavioral testbenches, constrained random stimulus, functional coverage, and assertions⁶
• UVM for development of modular, reusable, scalable testbenches; sequence-based stimulus, and verification methodology^7,8

With all these languages and other standards at play, it should be no surprise that use of hybrid or multi-language SoC testbenches is growing too. The 2011 merger between the Open SystemC Initiative (OSCI), the body responsible for the SystemC and TLM 1.0/2.0 standards, and Accellera, the body responsible for standardizing the UVM and initiating the standardization of SystemVerilog, could be viewed as a reflection of this trend. The merger was explained thus:

System, software and semiconductor design activities are converging to meet the increasing challenges to create complex system-on-chips (SoCs).

…

The relationship between OSCI's TLM-2.0 SystemC Transaction Level Modeling standard and Accellera's Universal Verification Methodology (UVM) standard exemplifies the synergy that exists between the two organizations.⁹

A direct result of this synergy is UVM Connect, which integrates all these standards to enable connections between TLM models written in SystemC and SystemVerilog. It also includes an API that allows SystemC, C, and C++ code to interact with and control the execution of UVM testbenches in SystemVerilog.

Requirements

Establishing a communications link between SystemC and SystemVerilog is nothing new. There have been plenty of implementations, papers, and proposals written describing how to interface SystemVerilog with a foreign language.^{10,11,12,13,14}

We believe UVM Connect differentiates itself by virtue of the unique requirements that drove its development, including:

• Open source, to foster broad industry acceptance and transparency.
• Portability across vendors, to protect user investment and allow vendors to differentiate with layered products.
• Must work without requiring modifications to existing standards, Accellera‟s UVM in particular.
• Allow models to fully exploit the features of the language in which they were written.
• Does not impose a foreign methodology nor require models or transactions to inherit from a base class, implement a conversion interface, etc.
• Supports the connection of existing TLM models in both SystemC and SystemVerilog without requiring their modification.

Having met all these requirements, we believe UVM Connect provides a natural solution to the mixed-language feature being discussed by the Accellera VIP Technical Steering Committee (TSC).