The Future of Semiconductors: Engineering in the Convergence Era

We’re entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine.

Device scaling still matters — but it no longer defines the industry’s trajectory.
Architecture, integration, verification, and automation do.

And the organizations that embrace this cross-domain, lifecycle-oriented mindset — with verification and agentic AI at the center — will define the next decade.

System-level scaling: Where the real action is

Moore’s Law didn’t “die.” What changed is the economic engine behind it. Transistors still shrink, but the cost-per-transistor advantage that powered decades of predictable scaling is no longer guaranteed.

Today, real breakthroughs come from system-level engineering — from the way we assemble, integrate, and optimize entire platforms:

• Disaggregating designs into chiplet-style components
• Hybrid bonding that pulls memory dramatically closer to compute
• 3DIC techniques (TSVs, wafer-to-wafer stacking, backside power delivery) that extend scaling into the vertical dimension
• HBM and advanced packaging architectures that break bandwidth ceilings
• Photonics to bypass electrical interconnect limits
• Coherency fabrics tying multi-die systems into unified engines

Chiplets still operate mostly within closed internal ecosystems today, but standards like UCIe are finally maturing, and by the end of the decade I expect the first true external chiplet vendors to emerge — limited, curated, but real.

The end of orthogonalization (where it’s breaking — and where it still holds)

One of the most underappreciated shifts is the erosion of the clean separation of
concerns that defined the 1990s and 2000s.

At the chip level, some of those abstractions still hold. RTL, timing, power, thermals, and software can still be reasoned about with reasonably clean boundaries. But even here, we see erosion:

• Multiple power domains cause power-state–dependent functional behavior
• Thermal gradients shift timing enough to affect correctness
• Mixed-signal blocks blur the digital/analog boundary
• Local workloads influence memory and coherency behavior

Chip-level orthogonalization isn’t gone — but it’s no longer airtight.

At the system level, however, orthogonalization has collapsed:

• Hybrid bonding changes timing
• Thermal drift alters latency and coherency
• Photonic bandwidth varies with temperature
• Software load changes physical behavior
• Cross-die interactions emerge between components from different vendors
• In 3DIC stacks, mechanical stress and warpage become functional variables