Visualizer Debug Environment provides a high-performance, high-capacity, tightly integrated debug environment for Simulation and Emulation. Waveform debug and source and connectivity debug for Verilog and VHDL are tightly integrated with class debug and UVM debug, with transaction viewing. Visualizer supports SystemVerilog, SystemC, C++ and C environments in the same way.
Visualizer supplies a complete debug experience in both live simulation debug and post simulation debug. One-click driver tracing and X tracing improve productivity.