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Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP
Webinar - Mar 11, 2026 by Luis Rodriguez
In this webinar we present a scalable methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models.
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Human-Centered Agentic AI Workflows for RTL Verification
Paper - Feb 27, 2026 by Harry Foster
The Questa One Agentic Toolkit extends the Questa One solution with human-centered agentic workflows that embed intelligence directly into these workflows, rather than isolated tools. By combining engine-native context, goal-driven agents, deliberate human-in-the-loop design, and open integration, the Questa One Agentic Toolkit provides a pragmatic path toward more adaptive and scalable productivity, supporting faster progress without sacrificing trust or rigor.
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Human-Centered Agentic AI Workflows for RTL Verification
Resource (Paper (.PDF)) - Feb 27, 2026 by Harry Foster
In this paper, you will learn that productivity challenges in modern semiconductor development stem less from individual tool limitations and more from process-level complexity across design creation, verification, and iteration. Agentic EDA addresses this shift by embedding intelligence directly into workflows that span creation and validation.
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AI Assisted FPU Verification Using Questa One SFV
Webinar - Feb 25, 2026 by Gerardo Nahum
One of the key components of the AI revolution is Floating Point Hardware design. Design targeting AI requires at times fast computing with low precision and at times very high precision in its calculations. In this webinar we show how Questa One AI assisted tools for Static Formal, help to generate full formal verification checkers for user defined functionality including floating-point operations.
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AI Assisted FPU Verification Using Questa One SFV
Resource (Slides (.PDF)) - Feb 25, 2026 by Gerardo Nahum
In this webinar we show how Questa One AI assisted tools for Static Formal, helps to generate full formal verification checkers for user defined functionality including floating-point operations.
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Smart Verification with AI/ML: Unleashing the Potential of AI within Functional Verification
Resource (Slides (.PDF)) - Feb 24, 2026 by Austin Mam
Leverage the power of AI and ML! Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allow engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.
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Verification IP: Delivering Accelerated Confidence
Resource (Slides (.PDF)) - Feb 24, 2026 by Gordon Allan
Learn about Verification IPs promise to enhance productivity and ease of use in the rapidly expanding landscape of complex interfaces and memory protocols, spanning SoC designs, 3D-IC chiplets, and FW/SW integration.
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Ensure High Quality RTL with Early Continuous Integration
Resource (Slides (.PDF)) - Feb 24, 2026 by Walter Gude
Learn the value of Continuous Integration (CI) during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
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Enhancing Productivity in Simulation-Based Functional Verification
Resource (Slides (.PDF)) - Feb 24, 2026 by Moses Satyasekaran
Improving productivity has become crucial for efficiently utilizing expensive human and grid resources in the functional verification process. Achieving the "done" state requires more than simulator performance—it demands a strategic focus on optimizing workflows, prioritizing tasks, and leveraging metrics to guide efforts. A productivity-driven approach ensures resources are deployed effectively, accelerating verification closure.
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Verification Academy Live: El Segundo
Seminar - Feb 24, 2026 by Joe Hupcey
This seminar explores technologies and techniques you can adopt to increase your verification productivity. We will cover: How the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains Benefits of an automated Continuous Integration flow to enhance RTL quality and streamline development processes Protecting against data corruption with formal security verification Latest advancements in RTL simulation
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Siemens at DVCon U.S. 2026
Resource (Verification Horizons Blog) - Feb 22, 2026 by Dennis Brophy
DVCon U.S. returns to a larger venue at the Hyatt Regency Santa Clara. The expanded rooms and exhibit hall are intended to support a program heavily focused on AI in verification. Siemens EDA will have a significant presence throughout the week. This includes a sponsored luncheon panel, a major conference keynote, technical papers, and multiple tutorials that advance the state of verification, agentic AI, CDC and RDC standardization, and HLS to FPGA cloud prototyping.
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Accelerating Verification Closure with Siemens DFT Verification Solutions
Resource (Slides (.PDF)) - Feb 19, 2026 by Jake Wiltgen
This session details how Siemens DFT-centric verification technology tackles these challenges by providing a unified platform streamlined to Tessent flows, delivering industry leading performance and enhanced user experience, and accelerating DFT verification closure while reducing cost and risk to reach DFT sign-off.
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Questa One: Arm Neoverse CSS RTL Signoff with CSS VIP and Software Aware VIP
Resource (Slides (.PDF)) - Feb 19, 2026 by Jalaj Gupta
A robust methodology to accelerate the development and verification of Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP and Arm Fast Models. The approach supports early software bring-up, including full UEFI and Linux bootup, while validating the RTL design and complex protocols like PCIe7, CXL4, HBM, and UCIe3 in simulation for fastest turnaround time.
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Introducing Questa One SFV - The Transformation of Static & Formal Powered by AI/ML
Resource (Slides (.PDF)) - Feb 19, 2026 by David Landoll
In today's fast-paced development schedules, engineers are constantly balancing innovation with efficiency. Questa One SFV, powered by AI/ML, is designed to streamline workflows, eliminate steep learning curves, and accelerate adoption. Learn how SFV can integrate into your current flow and improve productivity.
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Enhancing Productivity in Simulation-Based Functional Verification with Questa One
Resource (Slides (.PDF)) - Feb 19, 2026 by Sunil Sahoo
Questa™ One represents a next-generation smart verification solution designed to transform chip verification from a bottleneck into a competitive advantage. Built on principles of connected, data-driven, and scalable verification, Questa One unifies engines, workflows, and teams to deliver faster insights and higher confidence across simulation, static, formal, and coverage domains. By integrating AI-enhanced automation, predictive analytics, and unified debug and regression management.
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Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification
Webinar - Feb 18, 2026 by Jalaj Gupta
This session highlights what’s new in PCIe Gen7 security and demonstrates how Avery Verification IP-built on deep PCIe and UCIe verification expertise-enables early validation of TDISP and IDE functionality, comprehensive protocol and security coverage, and faster compliance, reducing risk and time-to-market for secure PCIe designs.
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Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification
Resource (Slides (.PDF)) - Feb 18, 2026 by Jalaj Gupta
PCIe® Gen7 delivers unprecedented bandwidth and introduces stronger security capabilities, including TDISP for device security and isolation, and IDE for end-to-end data encryption and integrity.
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Beyond Simulation: Unlocking Absolute Certainty in Hardware Design with Formal Verification
Resource (Verification Horizons Blog) - Feb 16, 2026 by Nicolae Tusinschi
Have you ever wondered how we can truly guarantee that the complex chips powering our world – from smartphones to self-driving cars – will always work flawlessly, even in the most obscure scenarios? It’s a question that keeps many engineers up at night, especially as designs grow exponentially more intricate. That’s precisely the challenge addressed in my recent paper, Achieving Mathematical Certainty in Design Verification with Formal .
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Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC
Resource (Slides (.PDF)) - Feb 11, 2026 by Kurt Takara
In this webinar, you will learn how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and filter functionally false positives.
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Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC
Webinar - Feb 11, 2026 by Kurt Takara
This webinar will discuss how Questa CDC Power Aware analysis can address this problem, as well as describe how Questa CDC combines exhaustive formal analysis with automated protocol assertions to prove safe crossings and filter functionally false positives.
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Close Coverage Faster with Questa One Sim's Unreachability Analysis
Webinar - Feb 05, 2026 by Justin Royse
Coverage closure remains the single largest challenge facing functional verification teams today, affecting 34% of both ASIC and FPGA design projects. As verification approaches completion, coverage scores plateau well short of project goals—a phenomenon commonly known as the "Last Mile problem." This webinar explores why traditional approaches to closing coverage gaps fall short and introduces automated unreachability analysis in Questa One Sim as a transformative solution.
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Close Coverage Faster with Questa One Sim's Unreachability Analysis
Resource (Slides (.PDF)) - Feb 05, 2026 by Justin Royse
This webinar explores why traditional approaches to closing coverage gaps fall short and introduces automated unreachability analysis in Questa One Sim as a transformative solution.
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Compute Subsystem RTL Signoff with CSS VIP and Software Aware VIP
Resource (Slides (.PDF)) - Feb 04, 2026 by Luis Rodriguez
This session highlights a robust methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 based and also RISC-V based Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models. Guest Presenter: Purna Mohanty – Signature IP
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Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification
Resource (Slides (.PDF)) - Feb 04, 2026 by Jalaj Gupta
In this session, you will learn more about Security Verification with Avery PCIe Verification IP and features in Avery PCIe Gen7.
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Verifying Chiplet Interconnects at Scale: UCIe® 3.0
Resource (Slides (.PDF)) - Feb 04, 2026 by Luis Rodriguez
This session highlights what’s new in UCIe 3.0 and explains how Avery UCIe Verification IP enables faster bring-up, deeper protocol coverage, and reduced risk by validating compliance, corner cases, and system-level behavior—helping teams confidently deliver robust chiplet-based silicon. Guest Presenter: Jie Ding – Ayar Labs