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Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator
Webinar - Feb 12, 2025 by Mark Carey
In this session, we explore the powerful smart regression features of collaborative browser-based data-driven verification. You will then learn how to harness the full potential of Questa Verification IQ to boost efficiency and productivity in your verification efforts, take advantage of automating the detection of design differences and optimize regression time by maximizing compute resources.
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Verification Academy Live: El Segundo
Seminar - Feb 06, 2025 by Joe Hupcey
Thursday, February 6th | 9:30 AM - 5:00 PM | El Segundo, CA This seminar will update you on technologies and techniques you can adopt to increase your verification productivity today. Specifically, we will cover: How the AI/ML paradigm shift enables functional verification productivity gains The benefits of an automated CI flow to enhance RTL quality and streamline development processes How to protect against data corruption with formal security verification Advancements in RTL simulation
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Streamlining FPU Verification with an Alternative to C-reference Model Approaches
Webinar - Feb 05, 2025 by Gerardo Nahum
In this session, you will be introduced to the Questa FPU application, explaining how it can quickly detect design inconsistencies and reduce verification time from months to days (based on an easy setup process).In this session, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation.
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Verification Academy Live: Silicon Valley
Seminar - Jan 30, 2025 by Joe Hupcey
Verification IP for UCIe, PCIe Gen 7, HBM4, and more Thursday, January 30th | 9:30 AM - 3:30 PM | Fremont, CA This seminar will show how to leverage next-gen verification IP to rapidly verify high-performance protocol designs being employed on today's 3DICs and SoCs.
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An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262
Webinar - Jan 29, 2025 by Ann Keffer
In this session, you will learn more about Siemens EDA functional safety concepts and tool flow. In addition, we will walk you through our closed-loop solution; from requirements gathering, FMEDA, safety analysis, fault injection and back to merging the results to generate the work products necessary for certification.
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Explore How to Protect Against Data Corruption with Formal Security Verification
Webinar - Jan 22, 2025 by Keerthi Devraj - Siemens EDA
In this session, you will learn about the importance of hardware security including; why robust hardware security is fundamental to all security applications, especially as hardware forms the backbone of critical systems and the implications of hardware breaches, which can lead to severe financial, reputational, and operational consequences.
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Unlocking the Power of QuestaSim and Visualizer Integration
Webinar - Jan 15, 2025 by Justin Royse
In this webinar, you will learn how you can get faster simulation runs, smaller simulation databases. We will also cover qrun which simplifies your scripting environment by bringing together compilation, optimization and elaboration into a single command and fewer switches. Then we will cover how you can get better coverage performance using our Next-Gen Coverage engine.
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Verification Process Overview
Session - Jan 10, 2025 by Harry Foster
This session, with five lessons shown in the tabs below, covers the Verification Process: where to start, what needs to be done, and when verification is complete. Learn about directed testing, constrained-random stimulus, and coverage metrics. Explore testbench tasks, component roles, and reuse strategies. Understand UVM test flow, from selection to completion. By the end, you’ll master effective verification strategies.
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Introduction to Functional Verification
Lesson - Jan 10, 2025 by Bob Oden
You will learn about the Verification Process, addressing three key questions. First, where to start? Even verifying a small design can be daunting. Starting right is crucial as it saves time and minimizes bug escapes. Second, what needs to be done? Each design has unique features to verify. Understanding required tasks is vital for planning, managing, and completing verification. Lastly, when is verification done? This common question arises as we near a project’s end.
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Introduction to Functional Verification
Resource (Slides Download) - Jan 10, 2025 by Bob Oden
You will learn about the Verification Process, addressing three key questions. First, where to start? Even verifying a small design can be daunting. Starting right is crucial as it saves time and minimizes bug escapes. Second, what needs to be done? Each design has unique features to verify. Understanding required tasks is vital for planning, managing, and completing verification. Lastly, when is verification done? This common question arises as we near a project’s end.
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Understanding the Two Main Testing Approaches
Lesson - Jan 10, 2025 by Harry Foster
You will learn about directed testing and constrained-random stimulus, the two main testing strategies. We’ll discuss where to apply each strategy and how to measure testing completeness using coverage metrics. By the end of this lesson, you’ll have a solid understanding of how to effectively apply these strategies in your verification process.
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Understanding the Two Main Testing Approaches
Resource (Slides Download) - Jan 10, 2025 by Harry Foster
You will learn about directed testing and constrained-random stimulus, the two main testing strategies. We’ll discuss where to apply each strategy and how to measure testing completeness using coverage metrics. By the end of this lesson, you’ll have a solid understanding of how to effectively apply these strategies in your verification process.
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What is a Reusable Testbench?
Lesson - Jan 10, 2025 by Tom Fitzpatrick
You will learn about testbench tasks, component roles, and customization for varied applications. You will also learn how to reuse components across projects, enabling efficient 'horizontal reuse'.
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What is a Reusable Testbench?
Resource (Slides Download) - Jan 10, 2025 by Tom Fitzpatrick
You will learn about testbench tasks, component roles, and customization for varied applications. You will also learn how to reuse components across projects, enabling efficient 'horizontal reuse'.
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How Can I Reuse Testbench Components?
Lesson - Jan 10, 2025 by Tom Fitzpatrick
You will learn how to build and customize reusable testbench components. Discover 'vertical reuse' from block level to system level in your project.
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How Can I Reuse Testbench Components?
Resource (Slides Download) - Jan 10, 2025 by Tom Fitzpatrick
You will learn how to build and customize reusable testbench components. Discover 'vertical reuse' from block level to system level in your project.
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UVM Test Flow
Lesson - Jan 10, 2025 by Bob Oden
You will learn the flow of a UVM test: selecting, starting, understanding stages, ending, and the roles of testbench components.
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UVM Test Flow
Resource (Slides Download) - Jan 10, 2025 by Bob Oden
You will learn the flow of a UVM test: selecting, starting, understanding stages, ending, and the roles of testbench components.
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Creating and Using a Test Plan
Session - Jan 10, 2025 by Bob Oden
This session, with two lessons shown in the tabs below, covers the purpose and content sources of a test plan. Learn how to finalize a test plan and use its fields to measure coverage achievement and identify gaps. By the end, you’ll understand how to effectively create and utilize a test plan for comprehensive verification.
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Creating a Test Plan
Lesson - Jan 10, 2025 by Bob Oden
You will learn the purpose and content sources of a test plan in this important lesson.
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Creating a Test Plan
Resource (Slides Download) - Jan 10, 2025 by Bob Oden
You will learn the purpose and content sources of a test plan in this important lesson.
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Test Plan Fields
Lesson - Jan 10, 2025 by Bob Oden
You will learn how to finalize a test plan and use its fields to measure coverage achievement and identify gaps.
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Test Plan Fields
Resource (Slides Download) - Jan 10, 2025 by Bob Oden
You will learn how to finalize a test plan and use its fields to measure coverage achievement and identify gaps.
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Data Types and Procedural Statements
Session - Jan 10, 2025 by Bob Oden
This session, with four lessons shown in the tabs below, covers SystemVerilog’s default data types, variable declaration, and type casting. Learn about the two basic array types, their usage, and indexing. Explore the array types available and the methods for their use. Understand selection, loop, and jump statements in SystemVerilog. By the end, you’ll have a solid grasp of these fundamental concepts.
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SystemVerilog Data Types
Lesson - Jan 10, 2025 by Bob Oden
You will learn SystemVerilog's default data types, variable declaration, and type casting in this informative session.