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17 Results

• Introducing Smart Verification: Unleashing the Potential of AI Within Functional Verification

  Conference - Jun 24, 2024 by Tom Fitzpatrick

  In this session, you will learn that leveraging the power of AI and ML, Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allowing engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.

• Accelerated Confidence in Interface Designs mixing Software Layers, Hardware Protocols, Physical Connections

  Conference - Jun 24, 2024 by Gordon Allan

  In this session, you will learn that today high performance compute fabrics are spread over multiple die, multiple packages, multiple cards and racks in the data center. They are linked together by layers of CPU-to-CPU, cache-to-cache, and network node-to-node infrastructure. Those connections are based on standardized protocols, always evolving and improving, and increasingly having both a hardware interaction of multiple layers, plus one or more software layers.

• Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove

  Conference - Jun 24, 2024 by Tom Fitzpatrick

  In this session, you will learn that the Portable Stimulus Standard (PSS) encourages verification engineers to focus on describing test scenarios, without worrying about the underlying target environment on which the test will ultimately be run. By describing the scenarios in terms of a randomizable schedule of actions, or behaviors that will execute, the test can easily be retargeted to different implementations for different environments.

• Challenges of Developing IPs for AI Chips

  Conference - Jun 24, 2024 by Tom Fitzpatrick

  Tom Fitzpatrick interviews Rambus VP of Engineering Susheel Tadikonda about the high-level D&V challenges of developing IPs for the new breed of AI accelerator chips; including the need to support a high-degree of IP configurability, 3DIC-specific protocol requirements that call for new levels of security for data in-motion and at rest.

• Mark your calendar for the 2024 DAC-Chips to Systems Conference

  Resource (Verification Horizons Blog) - May 28, 2024 by Harry Foster

  Get ready and mark your calendars for DAC 61 – the Chips to Systems Conference you won’t want to miss! As the ultimate event for all things chips to systems, DAC offers top-notch training, education, exhibits, and unbeatable networking opportunities for designers, researchers, tool developers, and vendors alike. This year, we’re thrilled to announce that Siemens is DAC’s first-ever Diamond Sponsor, shining bright at booth #2521.

• Verification of HPC Protocols and Memories

  Webinar - Mar 08, 2022 by Gordon Allan

  In this technical session we focus on the advances in PCI Express generation 6 protocol, and on the Compute Express Link (CXL) protocol.

• Verification of HPC Protocols and Memories

  Resource (Slides) - Mar 08, 2022 by Gordon Allan

  To enable High Performance Compute (HPC) architectures goals, there are new interconnect protocols, memory solutions, and storage connectivity solutions at all levels of the datacenter, from chip through package, board, backplane, module, and rack to facility level. New solutions change the game for design and verification, and demand expertise and comprehensive support from EDA.

• ‘The Dog Ate my RTL’ Doesn’t Work Anymore

  Webinar - Feb 15, 2022 by Joe Hupcey

  In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

• ‘The Dog Ate my RTL’ Doesn’t Work Anymore

  Resource (Slides) - Feb 15, 2022 by Joe Hupcey

  In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

• An Emulation Strategy for AI and ML Designs

  Resource (Slides) - Jul 15, 2019 by Vijay Chobisa

  The emergence of Artificial Intelligence is the “next big thing” in the overall economy and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges.

• Using Automation to Close the Loop Between Functional Requirements and their Verification

  Webinar - Aug 10, 2018 by Brian Craw

  This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.

• Using Automation to Close the Loop Between Functional Requirements and their Verification

  Resource (Slides) - Aug 10, 2018 by Brian Craw

  This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.

• Data Mining for SoC Level Performance

  Resource (Slides) - Jul 26, 2018 by Mark Olen

  This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.

• No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

  Resource (Recording) - Jul 26, 2018 by Kurt Takara

  In this session we will share a real world case study of how the customer applied Questa CDC at the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)

• Accelerating UVM-based Verification from Simulation to Emulation

  Resource (Slides) - Jul 24, 2017 by

• SystemVerilog OOP Basics used in UVM Verification

  Webinar - Jul 12, 2017 by Dave Rich

  In this session, you will learn some of the core concepts behind Object-Oriented Programming to help you get a better understand what a methodology like the UVM can do for you.

• Using the UVM Register Layer

  Resource (Slides) - Jun 22, 2012 by John Aynsley

  Slides from DAC 2012 where John Anysley from Doulos shares the Architecture of the Register Layer, The Register Model and Running Register Sequences.