Upcoming Webinar

Simulating AMD’s next-gen Versal Adaptive SoC devices using QuestaSim

Wednesday, July 24th - 8:00 AM US/Pacific

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13 Results

  • Mark your calendar for the 2024 DAC-Chips to Systems Conference

    Get ready and mark your calendars for DAC 61 – the Chips to Systems Conference you won’t want to miss! As the ultimate event for all things chips to systems, DAC offers top-notch training, education, exhibits, and unbeatable networking opportunities for designers, researchers, tool developers, and vendors alike. This year, we’re thrilled to announce that Siemens is DAC’s first-ever Diamond Sponsor, shining bright at booth #2521.

  • Verification of HPC Protocols and Memories

    In this technical session we focus on the advances in PCI Express generation 6 protocol, and on the Compute Express Link (CXL) protocol.

  • Verification of HPC Protocols and Memories

    To enable High Performance Compute (HPC) architectures goals, there are new interconnect protocols, memory solutions, and storage connectivity solutions at all levels of the datacenter, from chip through package, board, backplane, module, and rack to facility level. New solutions change the game for design and verification, and demand expertise and comprehensive support from EDA.

  • ‘The Dog Ate my RTL’ Doesn’t Work Anymore

    In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

  • ‘The Dog Ate my RTL’ Doesn’t Work Anymore

    In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

  • An Emulation Strategy for AI and ML Designs

    The emergence of Artificial Intelligence is the “next big thing” in the overall economy and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.

  • Data Mining for SoC Level Performance

    This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.

  • No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

    In this session we will share a real world case study of how the customer applied Questa CDC at the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)

  • Accelerating UVM-based Verification from Simulation to Emulation

  • SystemVerilog OOP Basics used in UVM Verification

    In this session, you will learn some of the core concepts behind Object-Oriented Programming to help you get a better understand what a methodology like the UVM can do for you.

  • Using the UVM Register Layer

    Slides from DAC 2012 where John Anysley from Doulos shares the Architecture of the Register Layer, The Register Model and Running Register Sequences.