UPCOMING WEBINAR

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific

LEARN MORE & REGISTER.

Search Results

Filters
Reset All

Filters

Topic

Content Type

Audience

Tags

Show More

Show Less

8 Results

  • Verification of HPC Protocols and Memories

    In this technical session we focus on the advances in PCI Express generation 6 protocol, and on the Compute Express Link (CXL) protocol.

  • Verification of HPC Protocols and Memories

    To enable High Performance Compute (HPC) architectures goals, there are new interconnect protocols, memory solutions, and storage connectivity solutions at all levels of the datacenter, from chip through package, board, backplane, module, and rack to facility level. New solutions change the game for design and verification, and demand expertise and comprehensive support from EDA.

  • ‘The Dog Ate my RTL’ Doesn’t Work Anymore

    In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.

  • Using Automation to Close the Loop Between Functional Requirements and their Verification

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.

  • Data Mining for SoC Level Performance

    This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.

  • No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

    In this session we will share a real world case study of how the customer applied Questa CDC at the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)

  • Accelerating UVM-based Verification from Simulation to Emulation