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Relieving the Parameterized Coverage Headache
Article - Jun 15, 2012 by Bryan Ramirez
Modern FPGA and ASIC verification environments use coverage metrics to help determine how thorough the verification effort has been. Practices for creating, collecting, merging and analyzing this coverage data is documented for designs operating in a single configuration. However, complications arise when parameters are introduced into the design, especially when creating customizable IP. This article discusses the coverage-related pitfalls and solutions when dealing with parameterized designs.
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Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs
Article - Jun 15, 2012 by Stephan van Beek, Sudhir Sharma, Sudeepa Prakash - MathWorks
Chip design and verification engineers often write as many as ten lines of test-bench code for every line of RTL code that is implemented in silicon. They can spend 50% or more of the design cycle on verification tasks. Despite this level of effort, nearly 60% of chips contain functional flaws and require re-spinning. Because HDL simulation is not sufficient to catch system-level errors, chip designers now employ FPGAs to accelerate algorithm creation and prototyping.
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Better Living Through Better Class-Based SystemVerilog Debug
Article - Jun 15, 2012 by Rich Edelman
SystemVerilog 1 UVM 2 class-based testbenches have become as complex as the hardware under test, and are evolving into large object-oriented software designs. The usual RTL debugging techniques must be updated to match this new complexity. Debugging tools are addressing these complexities, but this article will describe techniques and approaches that can be used to help debug these complex environments without advanced debug tools.
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Verification Horizons - Volume 8, Issue 2
Resource (Verification Horizons Archive) - Jun 15, 2012 by Tom Fitzpatrick
"On a recent visit to the Evergreen Aviation & Space Museum in Oregon, I had an opportunity to see some great examples of what, for their time, were incredibly complex pieces of engineering... those successes were the result of early failures where engineers learned the hard way...”
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AMS Design Configuration Schemes
Track - Jun 01, 2012 by Ahmed Eisawy
This track will introduce the various techniques available in Analog/Mixed-Signal (AMS) design environment to help understand how to efficiently utilize them. Understanding the challenges in AMS verification, will help learn how to properly address them, thus, creating an efficient design environment.
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Overview to AMS Configuration
Session - Jun 01, 2012 by Ahmed Eisawy
This session introduces the opposing powers in design methodologies and the concept of mixed-signal design environments. A high-level description of mixed-signal challenges is also provided along with the various available techniques that attempt to address these challenges.
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Introduction to Metrics
Session - Jun 01, 2012 by Harry Foster
This session provides an introduction and motivation for introducing metrics-driven processes into your flow.
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Analog/Mixed-Signal Domain
Session - Jun 01, 2012 by Ahmed Eisawy
This session introduces the definition for mixed-signal domain. A deeper-level description of the need for mixed-signal domain and the current challenges in verification and design. Then, addresses the three main areas for AMS design: functionality, robustness and reliability.
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The Driving Forces for Change
Session - Jun 01, 2012 by Andreas Meyer
This session examines the issues that are motivating change and the need for metrics-driven processes and discusses what is not working in today’s IP-based SoC design flows.
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Design Methodologies
Session - Jun 01, 2012 by Ahmed Eisawy
This session covers the 2 main flows used in mixed-signal design environments: bottom-up design flow and top-down design flow. In each case, the flow is presented along with its merits and demerits. Additionally, the balance as a methodology strategy is demonstrated to improve the end-product.
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Design Topologies
Session - Jun 01, 2012 by Ahmed Eisawy
This session covers the 2 main design topologies in mixed-signal SoC: analog-centric mixed-signal designs and digital-centric mixed-signal designs. In each case, the design nature and constraints are presented along with the various available approaches that can be used with their merits and demerits.
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What Can Metrics Tell Us?
Session - Jun 01, 2012 by Andreas Meyer
This session expands our discussion on what metrics can tell us by providing examples for various common processes within today’s SoC verification flow.
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Mixing Languages
Session - Jun 01, 2012 by Ahmed Eisawy
This session defines the language choices available in a mixed-signal design structure and how each choice impacts the performance and quality of the process. Then, introduces the concept of design reconfiguration and the available schemes to alter the design structure in constructive manners to help the mixed-signal verification performance which directly helps improve the quality of the design by allowing the designer to cover/test more areas of the design.
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What's Needed to Address the Problem?
Session - Jun 01, 2012 by Andreas Meyer
This session discusses four important aspects of a successful metrics-driven process: understanding the landscape, categorization, run-time control and reporting.
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Questa ADMS: AMS Configuration
Session - Jun 01, 2012 by Ahmed Eisawy
This session introduces Questa ADMS, and how this tool can be adapted in various topologies supporting the available methodologies with little or no impact on the design flow. Questa ADMS features and capabilities are explored to show how they can address the various challenges in mixed-signal SoC design. Customer success stories and testimonials are provided to show how successful Questa ADMS is being used in various design environments.
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What's Needed to Adopt Metrics?
Session - Jun 01, 2012 by Andreas Meyer
This session discusses important aspects of an implementation that should be considered when architecting a solution.
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Evolving Trends in Functional Verification
Resource (Slides (.PDF)) - Jun 01, 2012 by Harry Foster
2012 Wilson Research Group Functional Verification Study Results
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What to Expect After Adopting the Metrics
Session - Jun 01, 2012 by Andreas Meyer
This session provides a conclusion of what benefits to expect after you adopt metrics-driven processes.
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Metrics in SoC Verification
Track - Jun 01, 2012 by Andreas Meyer
In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.
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Analog Mixed-Signal Verification
Topic - Jun 01, 2012 by None
Today’s ICs increasingly rely on complex mixed-signal functionality with stringent performance and low power requirements for applications in segments including IoT, Automotive, Communications, and Industrials. Verification of these complex mixed-signal ICs is challenging due to the need to ensure that they meet demanding specifications with correct connectivity, functionality, and adequate system performance across analog/digital (A/D) interfaces on the chip. To address these challenges, verification teams need to run an increasing number of mixed-signal simulations at the top level as well as at the sub-system level. These mixed-signal simulation solutions need to be fast, accurate, easy to use, and seamlessly integrate into existing analog and digital verification flows.
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Introduction to UVM Connect
Session - May 31, 2012 by Adam Erickson
This session introduces UVM Connect and explains the benefits of adoption. It also reviews the principles and concepts behind the TLM1 and TLM2 standards and reviews the basic connection syntax and semantics of both SystemVerilog and SystemC.
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Introduction to UVM Connect
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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Connections
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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Connections
Session - May 31, 2012 by Adam Erickson
This session shows how to establish TLM-based connections between components in SystemVerilog and SystemC.
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Converters
Session - May 31, 2012 by Adam Erickson
This session shows how to write the converters that are needed to transfer transaction data across the language boundary.