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Improving FPGA Debugging with Assertions
Article - Sep 10, 2012 by Harry Foster
Here’s one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics.
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UVM Connect 2.2 Kit
Resource (Tarball) - Sep 07, 2012 by John Stickley
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Improve AMS Verification Performance
Track - Sep 01, 2012 by Ahmed Eisawy
This track will introduce various modeling practices available in an Analog/Mixed-Signal (AMS) design environment to help understand how to efficiently utilize them. Understanding the modeling tools available in AMS domain, will help learn how to properly address them, thus, help improve the AMS verification performance.
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Overview to Improve AMS Performance
Session - Sep 01, 2012 by Ahmed Eisawy
This session introduces the challenges in mixed-signal verification performance. A high-level description of the accuracy vs. performance/capacity tradeoffs is also provided along with the various available technologies that attempt to address the different areas of tradeoffs.
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AMS Engines
Session - Sep 01, 2012 by Ahmed Eisawy
This session covers the 2 main simulator technologies used in mixed-signal verification: AMS Simulation and Analog/Digital Co-Simulation. In each case, the technology is presented along with its merits and demerits. Additionally, capabilities expected from AMS engines are presented.
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Modeling Abstraction
Session - Sep 01, 2012 by Ahmed Eisawy
This session defines the language choices available in a mixed-signal design structure and how each choice impacts the performance and quality of the results. Then, introduces the concept of abstraction which helps define only a subset of effects that are of interest to each design phase. Abstraction helps the mixed-signal verification performance which directly helps improve the quality of the design by allowing the designer to cover/test more behaviors of the design.
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AMS Modeling Guidance
Session - Sep 01, 2012 by Ahmed Eisawy
This session attempts to offer some general guidelines in developing models for the various analog and mixed-signal domains to achieve the optimum design flow to meet the requirements with reasonable resources. The session also covers some of the "good modeling practices" and comparing them to the "bad modeling practices" oftentimes a model developer would fall into.
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Questa ADMS: AMS Performance
Session - Sep 01, 2012 by Ahmed Eisawy
This session introduces Questa ADMS, and how this tool can be adapted in existing design flows supporting the available methodologies with little or no impact on the design flow, supporting virtually all language standards with a variety of features and capabilities to help accurately and efficiently model and verify complex mixed-signal designs to reach the goal of successful first tape-out using reasonable resources.
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FPGA Verification Capabilities
Track - Aug 30, 2012 by Ray Salemi
This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.
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Introduction from Harry Foster
Session - Aug 30, 2012 by Harry Foster
This session is an introduction to various code coverage metrics and how to apply them.
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Overview and Welcome
Session - Aug 30, 2012 by Ray Salemi
This session is an introduction to the seven steps for evolving your FPGA verification capabilities.
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Code Coverage
Session - Aug 30, 2012 by Ray Salemi
This session is an introduction to various code coverage metrics and how to apply them.
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Test Planning
Session - Aug 30, 2012 by Ray Salemi
This session shows how you can create a test plan that systematically captures all the functionality in your design so you can test it.
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Applied Assertions
Session - Aug 30, 2012 by Ray Salemi
This session discusses how to use assertions in a design, and then demonstrates how to insatiate an OVL checker into a VHDL design.
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Transactions
Session - Aug 30, 2012 by Ray Salemi
This session shows you how to create a transaction level testbench using modules instead of object. You will quickly have a testbench where modules talk to each other using transactions instead of signals.
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Self-Checking Testbenches
Session - Aug 30, 2012 by Ray Salemi
This session demonstrates how to combine predictors and comparators to form a self-checking testbench.
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Automatic Stimulus
Session - Aug 30, 2012 by Ray Salemi
This session introduces constrained-random stimulus for automatic stimulus generation.
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Functional Coverage
Session - Aug 30, 2012 by Ray Salemi
This session shows you how to implement functional coverage using SystemVerilog covergroups.
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Using the UVM Register Layer
Resource (Slides (.PDF)) - Jun 22, 2012 by John Aynsley
Slides from DAC 2012 where John Anysley from Doulos shares the Architecture of the Register Layer, The Register Model and Running Register Sequences.
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Siemens EDA has Accellera's Latest Standard Covered
Article - Jun 15, 2012 by Darron May
If you can't measure something, you can't improve it. For years, verification engineers have used "coverage" as a way to measure completeness of the verification effort. Of course, there are many types of coverage, from different types of code coverage to functional coverage, as well as many tools, both dynamic and static, that provide coverage information.
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Is Intelligent Testbench Automation For You?
Article - Jun 15, 2012 by Mark Olen
Intelligent Testbench Automation (iTBA) is being successfully adopted by more verification teams every day. There have been multiple technical papers demonstrating successful verification applications and panel sessions comparing the merits to both Constrained Random Testing (CRT) and Directed Testing (DT) methods. Technical conferences including DAC, DVCon, and others have joined those interested in better understanding this new technology.
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Automated Generation of Functional Coverage Metrics for Input Stimulus
Article - Jun 15, 2012 by Mike Andrews - Siemens EDA
Questa inFact allows for graphical definition of the coverage goals and can, with the 10.1 release, automatically generate SystemVerilog covergroups from this definition, including the exclusions needed to accurately represent the achievable coverage. This article describes how this capability can simplify the definition of more comprehensive stimulus coverage metrics.
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Targeting Internal-State Scenarios in an Uncertain World
Article - Jun 15, 2012 by Matthew Ballance
The challenges inherent in verifying today's complex designs are widely understood. Just identifying and exercising all the operating modes of one of today's complex designs can be challenging. Creating tests that will exercise all these input cases is, challenging and labor-intensive. Using directed-test methodology, is challenging to create sufficiently-comprehensive tests to ensure design quality, due to the amount of engineering effort needed to design, implement, and manage the test suite.
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Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces
Article - Jun 15, 2012 by Jim Kenney - Siemens EDA
With the majority of designs today containing one or more embedded processors, the verification landscape is transforming as more companies grapple with the limitations of traditional verification tools. Comprehensive verification of multi-core SoCs cannot be accomplished without including the software that will run on the hardware. Emulation has the speed and capacity to do this before the investment is made in prototypes or silicon.
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On the Fly Reset
Article - Jun 15, 2012 by Mark Peryer
A common verification requirement is to reset a design part of the way through a simulation to check that it will come out of reset correctly and that any non-volatile settings survive the process. Almost all testbenches are designed to go through some form of reset and initialization process at their beginning, but applying reset at a mid-point in the simulation can be problematic.