Search Results
Filters
Advanced Search
2143 Results
-
Questa Simulation: Assertions
Demo - Feb 10, 2010 by Chuck Seeley
This session will demonstrate how assertions can be used in simulation.
-
Questa Formal Verification
Demo - Feb 10, 2010 by Mark Eslinger
This session will demonstrate how assertions can be used in formal verification.
-
Verification Horizons - Volume 6, Issue 1
Resource (Verification Horizons Archive) - Feb 01, 2010 by Tom Fitzpatrick
“One of my favorite things about this week (DVCon) is the opportunity to meet new friends (and catch up with old friends, too), and I’d love to hear in person what you think about the conference, Verification Horizons, or the industry in general.”
-
Industry Perspective & Opportunities in ABV
Webinar - Jan 15, 2010 by Harry Foster
In this session, you will learn about Industry Perspective and Opportunities in ABV.
-
Verification Horizons - Volume 5, Issue 3
Resource (Verification Horizons Archive) - Dec 01, 2009 by Tom Fitzpatrick
“...it occurred to me that relying on good solid work that others have done is often the key to productivity...since it lets us focus on what we need to and lets us avoid wasting time and resources...”
-
Verification Horizons - Volume 5, Issue 2
Resource (Verification Horizons Archive) - Jul 01, 2009 by Tom Fitzpatrick
“The key to teamwork is to have everyone working together. In verification that means starting with a plan so that everyone knows what they’re doing and progress can be measured effectively.”
-
Verification Horizons - Volume 5, Issue 1
Resource (Verification Horizons Archive) - Feb 01, 2009 by Tom Fitzpatrick
“In the winter in New England, it’s important to stay warm and be thankful for friendly neighbors and family to help in times of need. In a stormy economy, it’s even more important to protect yourself from the “cold” of risk in your verification process.”
-
Verification Horizons - Volume 4, Issue 3
Resource (Verification Horizons Archive) - Oct 01, 2008 by Tom Fitzpatrick
“From its inception, we have always envisioned OVM as a “methodology platform,” in that it provides the infrastructure necessary to incorporate additional technologies in a unified way to extend existing verification strategies.”
-
Verification Horizons - Volume 4, Issue 2
Resource (Verification Horizons Archive) - Jun 01, 2008 by Tom Fitzpatrick
“If you’re going to be at DAC, ...stop by the Mentor booth, and feel free to ask for me if you’d like to say “hi.” We’d love the opportunity to talk to you about how the Mentor team can help you experience “the thrill of victory” on your next project.”
-
Verification Horizons - Volume 4, Issue 1
Resource (Verification Horizons Archive) - Feb 01, 2008 by Tom Fitzpatrick
“...my dad, who was an analog designer, used to tell me “it’s an analog world” to convince me that the “digital stuff” I was learning would never be sufficient to build everything. As Mark Twain said, “the older I’ve gotten, the smarter my father has become.”
-
Verification Horizons - Volume 3, Issue 4
Resource (Verification Horizons Archive) - Oct 01, 2007 by Tom Fitzpatrick
“...change isn’t always a bad thing. In our industry, it’s essential. One of the biggest changes recently is the announcement in August of Mentor Graphics and Cadence working together to deliver the Open Verification Methodology (OVM).”
-
Verification Horizons - Volume 3, Issue 2
Resource (Verification Horizons Archive) - Jun 01, 2007 by Tom Fitzpatrick
"In the case of Verification Horizons, success is defined in terms of providing interesting, educational and sometimes entertaining articles for your enjoyment and edification.”
-
Verification Horizons - Volume 3, Issue 1
Resource (Verification Horizons Archive) - Feb 01, 2007 by Tom Fitzpatrick
“...we look forward to some exciting times in 2007. There’s a lot going on both here at Mentor and within the industry to advance the frontiers of verification technology, and as always, we’ll be here to help keep you on the leading edge.”
-
Verification Horizons - Volume 2, Issue 3
Resource (Verification Horizons Archive) - Sep 01, 2006 by Tom Fitzpatrick
“In keeping with our DAC mythbusting theme, we are focusing this issue on looking at various myths about verification and setting things straight.”
-
Verification Horizons - Volume 2, Issue 2
Resource (Verification Horizons Archive) - Jul 01, 2006 by Tom Fitzpatrick
“Please make sure to come by and see us at DAC in July. We’ll be happy to talk more about the Advanced Verification Methodology, and any of the articles recently appearing in Verification Horizons.”
-
Verification Horizons - Volume 2, Issue 1
Resource (Verification Horizons Archive) - Feb 01, 2006 by Tom Fitzpatrick
“I encourage you to take a moment to help us make Verification Horizons more informative and enjoyable for you. In the meantime, we’ll be hard at work putting the next issue together while we continue to expand the horizons of verification.”
-
Verification Horizons - Volume 1, Issue 1
Resource (Verification Horizons Archive) - Nov 01, 2005 by Tom Fitzpatrick
“Each issue will include several in-depth technical articles about the latest advances in verification technology and methodology, as well as some timely tips for making better use of the tools you may currently have.”
-
Low Power
Topic - by Gabriel Chidolue
Low Power verification enables early (RTL) verification of active power management applied to a complex design, to ensure that the power management architecture and behavior are correct and that the design will operate correctly under active power management. Power Aware techniques simplify the verification process through a comprehensive suite of static checkers for checking the consistency of the power management architecture and dynamic checks for automated error detection. Utilizing Low Power standards provide visualization of power management architecture and behavior, coverage data collection, and test plan generation for power states and state transitions. Based on the UPF for specification of active power management, Power Aware integrates well with other UPF-based tools to support multi-tool and multi-vendor low power design and verification flows.
-
Clock-Domain Crossing
Topic - by Chris Giles
Designers increasingly use advanced multi-clock architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has more than one clock domain does not accurately model the silicon behavior related to the transfer of data between asynchronous clock domains. As a consequence, simulation does not accurately predict silicon functionality, risking show-stopper bug escapes due to metastability. Metastability is a phenomenon that can cause system failures in digital devices when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This topic area focuses on advanced techniques to find clock-domain crossing errors before they escape into silicon.
-
Questa Design Solutions
Topic - by Chris Giles
Questa Design Solutions is an automated and integrated suite of verification tools for designers to improve initial RTL quality. Design Solutions analyzes code at the design stage to detect bugs early, to improve efficiency, enhance development predictability and ease pressure on schedules.
-
Assertions
Topic - by Harry Foster
A verification engineer plays a critical role in the development of complex electronic systems, ensuring that these systems meet the desired functionality and adhere to the design specifications. One powerful tool in the verification engineer's arsenal is the use of assertions. Assertions are statements or properties embedded within the verification environment that help identify design bugs and verify the correctness of the system.
-
UVM Framework
Topic - by Bob Oden
The Universal Verification Methodology Framework (UVMF) is an advanced and comprehensive toolset that extends the capabilities of UVM, the Universal Verification Methodology. UVMF provides a robust and structured approach to verification, offering a wide range of pre-built components, utilities, and testbenches that accelerate and simplify the verification process. With UVMF's flexible architecture, verification engineers can effortlessly customize and integrate the components into their specific projects, fostering reusability and scalability. By leveraging UVMF, verification teams can significantly reduce development time, enhance collaboration, and ensure the delivery of high-quality, error-free semiconductor designs to meet the ever-increasing demands of the electronics industry.
-
Simulation
Topic - by Moses Satyasekaran
Simulation plays a pivotal role in the digital design and verification process. Its primary purpose is to validate whether the design being created functions according to the specified requirements. By running simulations early in the design phase, potential issues can be identified, thus minimizing the need for extensive code revisions. Simulations can be performed at different levels of abstraction and at various stages throughout the design process.
-
Reset-Domain Crossing
Topic - by Chris Giles
The high-level complexities of modern System On Chip (SoC) designs have created a complex architecture of multiple asynchronous reset sources. It is imperative to ensure that the design is reset accurately under all modes of operation. Such complex reset interactions asserting at the transmitting flop may violate setup and hold time considerations in receiving flop in different asynchronous reset domain and cause metastable data at the output of receiving flop resulting in reset domain crossings. A comprehensive and precise analysis is required to not only identify such crossings causing real and critical issues but also avoid reporting false bugs. This topic area focuses on advanced techniques to find reset-domain crossing errors in efficient way before they escape into silicon.
-
Verification IP
Topic - by Gordon Allan
Avery Verification IP (VIP) plays a crucial role in ensuring the success of complex semiconductor designs by offering a wide range of benefits and a compelling value proposition. Avery Verification IP provides pre-verified and reusable components, tools, and methodologies that enable efficient and thorough verification of electronic designs.