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Targeting Internal-State Scenarios in an Uncertain World
Article - Jun 15, 2012 by Matthew Ballance
The challenges inherent in verifying today's complex designs are widely understood. Just identifying and exercising all the operating modes of one of today's complex designs can be challenging. Creating tests that will exercise all these input cases is, challenging and labor-intensive. Using directed-test methodology, is challenging to create sufficiently-comprehensive tests to ensure design quality, due to the amount of engineering effort needed to design, implement, and manage the test suite.
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Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces
Article - Jun 15, 2012 by Jim Kenney - Siemens EDA
With the majority of designs today containing one or more embedded processors, the verification landscape is transforming as more companies grapple with the limitations of traditional verification tools. Comprehensive verification of multi-core SoCs cannot be accomplished without including the software that will run on the hardware. Emulation has the speed and capacity to do this before the investment is made in prototypes or silicon.
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On the Fly Reset
Article - Jun 15, 2012 by Mark Peryer
A common verification requirement is to reset a design part of the way through a simulation to check that it will come out of reset correctly and that any non-volatile settings survive the process. Almost all testbenches are designed to go through some form of reset and initialization process at their beginning, but applying reset at a mid-point in the simulation can be problematic.
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Relieving the Parameterized Coverage Headache
Article - Jun 15, 2012 by Bryan Ramirez
Modern FPGA and ASIC verification environments use coverage metrics to help determine how thorough the verification effort has been. Practices for creating, collecting, merging and analyzing this coverage data is documented for designs operating in a single configuration. However, complications arise when parameters are introduced into the design, especially when creating customizable IP. This article discusses the coverage-related pitfalls and solutions when dealing with parameterized designs.
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Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs
Article - Jun 15, 2012 by Stephan van Beek, Sudhir Sharma, Sudeepa Prakash - MathWorks
Chip design and verification engineers often write as many as ten lines of test-bench code for every line of RTL code that is implemented in silicon. They can spend 50% or more of the design cycle on verification tasks. Despite this level of effort, nearly 60% of chips contain functional flaws and require re-spinning. Because HDL simulation is not sufficient to catch system-level errors, chip designers now employ FPGAs to accelerate algorithm creation and prototyping.
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Better Living Through Better Class-Based SystemVerilog Debug
Article - Jun 15, 2012 by Rich Edelman
SystemVerilog 1 UVM 2 class-based testbenches have become as complex as the hardware under test, and are evolving into large object-oriented software designs. The usual RTL debugging techniques must be updated to match this new complexity. Debugging tools are addressing these complexities, but this article will describe techniques and approaches that can be used to help debug these complex environments without advanced debug tools.
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Verification Horizons - Volume 8, Issue 2
Resource (Verification Horizons Archive) - Jun 15, 2012 by Tom Fitzpatrick
"On a recent visit to the Evergreen Aviation & Space Museum in Oregon, I had an opportunity to see some great examples of what, for their time, were incredibly complex pieces of engineering... those successes were the result of early failures where engineers learned the hard way...”
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Introduction to Metrics
Session - Jun 01, 2012 by Harry Foster
This session provides an introduction and motivation for introducing metrics-driven processes into your flow.
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The Driving Forces for Change
Session - Jun 01, 2012 by Andreas Meyer
This session examines the issues that are motivating change and the need for metrics-driven processes.
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What Can Metrics Tell Us?
Session - Jun 01, 2012 by Andreas Meyer
This session expand our discussion on what metrics can tell us by providing examples for various common processes within today’s SoC verification flow.
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What's Needed to Address the Problem?
Session - Jun 01, 2012 by Andreas Meyer
This session discusses four important aspects of a successful metrics-driven process.
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What's Needed to Adopt Metrics?
Session - Jun 01, 2012 by Andreas Meyer
This session discusses important aspects of an implementation that should be considered when architecting a solution.
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Evolving Trends in Functional Verification
Resource (Slides (.PDF)) - Jun 01, 2012 by Harry Foster
2012 Wilson Research Group Functional Verification Study Results
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What to Expect After Adopting the Metrics
Session - Jun 01, 2012 by Andreas Meyer
This session provides a conclusion of what benefits to expect after you adopt metrics-driven processes.
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Metrics in SoC Verification
Track - Jun 01, 2012 by Andreas Meyer
In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.
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Introduction to UVM Connect
Session - May 31, 2012 by Adam Erickson
This session introduces UVM Connect and explains the benefits of adoption.
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Introduction to UVM Connect
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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Connections
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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Connections
Session - May 31, 2012 by Adam Erickson
This session shows how to establish connections between components.
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Converters
Session - May 31, 2012 by Adam Erickson
This session shows how to write the converters that are needed to transfer transaction data.
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Converters
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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UVM Command API
Session - May 31, 2012 by Adam Erickson
This session shows how control key aspects of UVM simulation from SystemC.
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UVM Command API
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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UVM Connect User Guide
Resource (Reference Documentation) - May 31, 2012 by Adam Erickson
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UVM 1.1b Class Reference
Resource (Reference Documentation) - May 21, 2012 by
v1.1b The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.