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Better Living Through Better Class-Based SystemVerilog Debug

Article - Jun 15, 2012 by Rich Edelman

SystemVerilog 1 UVM 2 class-based testbenches have become as complex as the hardware under test, and are evolving into large object-oriented software designs. The usual RTL debugging techniques must be updated to match this new complexity. Debugging tools are addressing these complexities, but this article will describe techniques and approaches that can be used to help debug these complex environments without advanced debug tools.
Verification Horizons - Volume 8, Issue 2

Resource (Verification Horizons Archive) - Jun 15, 2012 by Tom Fitzpatrick

"On a recent visit to the Evergreen Aviation & Space Museum in Oregon, I had an opportunity to see some great examples of what, for their time, were incredibly complex pieces of engineering... those successes were the result of early failures where engineers learned the hard way...”
Introduction to Metrics

Session - Jun 01, 2012 by Harry Foster

This session provides an introduction and motivation for introducing metrics-driven processes into your flow.
The Driving Forces for Change

Session - Jun 01, 2012 by Andreas Meyer

This session examines the issues that are motivating change and the need for metrics-driven processes.
What Can Metrics Tell Us?

Session - Jun 01, 2012 by Andreas Meyer

This session expand our discussion on what metrics can tell us by providing examples for various common processes within today’s SoC verification flow.
What's Needed to Address the Problem?

Session - Jun 01, 2012 by Andreas Meyer

This session discusses four important aspects of a successful metrics-driven process.
What's Needed to Adopt Metrics?

Session - Jun 01, 2012 by Andreas Meyer

This session discusses important aspects of an implementation that should be considered when architecting a solution.
Evolving Trends in Functional Verification

Resource (Slides (.PDF)) - Jun 01, 2012 by Harry Foster

2012 Wilson Research Group Functional Verification Study Results
What to Expect After Adopting the Metrics

Session - Jun 01, 2012 by Andreas Meyer

This session provides a conclusion of what benefits to expect after you adopt metrics-driven processes.
Metrics in SoC Verification

Track - Jun 01, 2012 by Andreas Meyer

In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.
Introduction to UVM Connect

Session - May 31, 2012 by Adam Erickson

This session introduces UVM Connect and explains the benefits of adoption.
Introduction to UVM Connect

Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
Connections

Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
Connections

Session - May 31, 2012 by Adam Erickson

This session shows how to establish connections between components.
Converters

Session - May 31, 2012 by Adam Erickson

This session shows how to write the converters that are needed to transfer transaction data.
Converters

Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
UVM Command API

Session - May 31, 2012 by Adam Erickson

This session shows how control key aspects of UVM simulation from SystemC.
UVM Command API

Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
UVM Connect User Guide

Resource (Reference Documentation) - May 31, 2012 by Adam Erickson
UVM 1.1b Class Reference

Resource (Reference Documentation) - May 21, 2012 by

v1.1b The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
UVM Connect 2.1.4 Kit

Resource (Tarball) - Feb 20, 2012 by John Stickley
Verification Horizons - Volume 8, Issue 1

Resource (Verification Horizons Archive) - Feb 01, 2012 by Tom Fitzpatrick

"Our kitchen renovation is nearly complete... Just as with verification, the key is to have a plan... take as many contingencies into account as you can... and... be able to handle constrained random stimulus.”
UVM 1.1a Class Reference

Resource (Reference Documentation) - Dec 01, 2011 by

v1.1a The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
Verification Horizons - Volume 7, Issue 3

Resource (Verification Horizons Archive) - Nov 01, 2011 by Tom Fitzpatrick

"I find myself thinking of how this (kitchen upgrade) relates to upgrading a verification methodology because I’m sure that, by now, you know that that’s how my mind works.”
Testbench Co-Emulation: SystemC & TLM-2.0

Track - Oct 27, 2011 by John Stickley

This track advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements.