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UVM Register Model CSV Example
Resource (Reference Documentation) - Aug 15, 2013 by Tom Fitzpatrick
The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication.
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Automate UVM Register Models
Webinar - Aug 15, 2013 by Tom Fitzpatrick
In this session, you will be introduced to the UVM Register Assistant that will show how to generate correct-by-construction register models and tests from a register specification.
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Verification Horizons - Volume 9, Issue 2
Resource (Verification Horizons Archive) - Jun 01, 2013 by Tom Fitzpatrick
"Building a theater set is not unlike what we do as verification engineers. It involves modeling the “real world,” often at a higher level of abstraction, and it has hard deadlines.”
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Interviewing a Verification Engineer
Article - Jun 01, 2013 by Akiva Michelson - Ace Verification
A key challenge today is choosing the right staff for achieving excellent verification results. Indeed, the defining moment for most projects is when the staff is selected, since the right combination of skills and personality can lead to outstanding technical outcomes (while the wrong combination can lead to disaster). Verification engineers differ significantly from other engineers in terms of skill sets required for success.
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Non-invasive Software Verification Using Vista Virtual Platforms
Article - Jun 01, 2013 by Alex Rozenman, Vladimir Pilko, Nilay Mitash - Siemens EDA
With the SoCs now supporting Multi-Core processors, complex ASICs and combinations that include systems on a board, SoC implementations now become an ever-growing challenge for software development. Software development has to be supported not only by the inclusion of an RTOS, but, many SoC providers now have to leverage upon the Bare-Metal concept to achieve the necessary demands of today's SoCs.
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QVM: Enabling Organized, Predictable, and Faster Verification Closure
Article - Jun 01, 2013 by Pradeep Salla
Until recently, the semiconductor industry religiously followed Moore's Law by doubling the number of transistors on a given die approximately every two years. This predictable growth allowed ecosystem partners to plan and deal with rising demands on tools, flows and methodologies. Then came the mobile revolution, which opened up new markets and further shifted the industry's focus to consumers.
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Verifying High Speed Peripheral IPs
Article - Jun 01, 2013 by Sreekanth Ravindran, Chakravarthi M.G. - Mobiveil
In this article, Silicon IP and platform enabled solution provider Mobiveil shares its story of verifying high speed bus protocol standards like PCI Express and Serial RapidIO, including what considerations are required when verifying high speed designs.
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Confidence in the Face of the Unknown: X-state Verification
Article - Jun 01, 2013 by Kaowen Liu - MediaTek Inc., Roger Sabbagh - Siemens EDA
Unknown signal values in simulation are represented as X-state logic levels, while the same X-states are interpreted as don't care values by synthesis. This can result in the hazardous situation where silicon behaves differently than what was observed in simulation. Although the general awareness of X-state issues among designers is good, gotchas remain a risk that traditional verification flows are not well equipped to guard against.
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Making it Easy to Deploy the UVM
Article - Jun 01, 2013 by Dr. Christoph Sühnel - Frobas GmbH
This article describes an UVM approach reducing testbench implementation effort, guaranteeing an early success and streamlining the processing of the test results. Depending on the number of functional interfaces and the design complexity up to 6 weeks of implementation effort or even more can be saved. A runnable UVM testbench will be handed over to the verification team at the very beginning of the project.
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NoC Generic Scoreboard VIP
Article - Jun 01, 2013 by François Cerisier, Mathieu Maisonneuve - TVS
The increase of SoC complexity with more cores, IPs and other subsystems has led SoC architects to demand more from the main interconnect or network-on-chip (NoC), which is thus becoming a key component of the system.
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Flexible UVM Components: Configuring Bus Functional Models
Article - Jun 01, 2013 by Gunther Clasen - Ensilica
This article shows a way to write BFMs in such a way that they can be configured like any other UVM component using uvm_config_db. This allows a uniform configuration approach and eases reuse. All code examples use UVM, but work equally with the set_config_*() functions in OVM.
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Monitors, Monitors Everywhere – Who Is Monitoring the Monitors
Article - Jun 01, 2013 by Rich Edelman
The reader of this article should be interested in predicting or monitoring the behavior of his hardware. This article will review phase-level monitoring, transaction-level monitoring, general monitoring, in-order and out-of-order transaction-level monitors, A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated. Under certain AXI usages, problems arise.
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The Need for Speed: Understanding Design Factors that Make Multi-core Parallel Simulations Efficient
Article - Jun 01, 2013 by Shobana Sudhakar
The intent of this article is to educate customers and guide them to understand what makes a design multicore friendly. This can help customers write designs and testbenches to be more suited for parallel simulations. Cases of success and failures of QuestaSim MC2 deployments and the lessons learned from them form the basis of our analysis and substantiate our suggestions in this article.
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An Enhanced UPF Example
Session - May 31, 2013 by Chuck Seeley
This session presents an extended example illustrating the usage of the UPF 2.0 features of IEEE Std 1801 UPF for specification of the power management architecture for a simple design.
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Using Supply Sets
Session - Apr 29, 2013 by Chuck Seeley
This session presents the UPF 2.0 concept of a “supply set” and the related commands and options used for defining and using supply sets.
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UPF 2.0 Enhancements
Session - Apr 08, 2013 by Chuck Seeley
This session presents UPF 2.0 commands and options that improve usability and provide greater flexibility.
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A Simple UPF Example
Session - Apr 08, 2013 by Chuck Seeley
This session presents an extended example illustrating the usage of the UPF 1.0 subset.
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Getting Started with UPF
Session - Apr 08, 2013 by Erich Marschner
This session presents the core commands and options in UPF 1.0 subset.
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Introduction to Power Aware Verification
Session - Apr 08, 2013 by Erich Marschner
This session introduces the IEEE Std 1801 Unified Power Format (UPF).
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Overview of UPF
Session - Apr 08, 2013 by Erich Marschner
This session gives a quick, high-level overview of the evolution of the UPF standard.
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Power Aware Verification
Track - Apr 05, 2013 by Erich Marschner
This track introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.
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Functional Verification Study - 2012
Session - Apr 01, 2013 by Harry Foster
In this session, Harry Foster highlights the key findings from the 2012 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
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UVM 1.1d Class Reference
Resource (Reference Documentation) - Mar 07, 2013 by
v1.1d The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
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Using Formal Analysis to Block and Tackle
Article - Feb 25, 2013 by Paul B. Egan - Rockwell Automation
This article will explain how we applied formal analysis at the block level, extended this to full chip and describe how we significantly reduced verification time at both the block and chip level. Just like a block and tackle provides a mechanical advantage, the formal connectivity flow provides a verification advantage
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Bringing Verification and Validation under One Umbrella
Article - Feb 25, 2013 by Hans Van Der Schoot
The standard practice of developing RTL verification and validation platforms as separate flows, forgoes large opportunities to improve productivity and quality that could be gained through the sharing of modules and methods between the two. Bringing these two flows together would save an immense amount of duplicate effort and time while reducing the introduction of errors, because less code needs to be developed and maintained.