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Stopping a Sequence
Chapter - Mar 31, 2014 by Verification Methodology Team
Once started, sequences should not be stopped.
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Virtual Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
A virtual sequence is a sequence which controls stimulus generation using several sequencers.
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Slave Sequences (Responders)
Chapter - Mar 31, 2014 by Verification Methodology Team
A slave sequence is used with a driver that responds to events on an interface rather than initiating them. This type of functionality is usually referred to as a responder.
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Wait for a Signal
Chapter - Mar 31, 2014 by Verification Methodology Team
In the general case, synchronizing to hardware events is taken care of in UVM testbenches by drivers (proxy & BFM) and monitors (proxy & BFM).
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Interrupt Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
In hardware terms, an Interrupt is an event which triggers a new thread of processing.
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Virtual Sequencers (Not Recommended)
Chapter - Mar 31, 2014 by Verification Methodology Team
A virtual sequence is a sequence which controls a stimulus generation process using several sequencers.
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Command Line Processor
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM command line processor is used to interact with plusargs. Several plusargs are pre-defined and part of the UVM standard.
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Transaction Methods
Chapter - Mar 31, 2014 by Verification Methodology Team
When working with data object classes derived from uvm_objects, including ones derived from uvm_transactions, uvm_sequence_items and uvm_sequences, there are a number of methods which are defined for common operations on the data objects properties.
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End of Test
Chapter - Mar 31, 2014 by Verification Methodology Team
A UVM testbench, if is using the standard phasing, has a number of zero time phases to build and connect the testbench, then a number of time consuming phases, and finally a number of zero time cleanup phases.
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UVM Driver
Chapter - Mar 30, 2014 by Verification Methodology Team
The UVM driver is responsible for communicating at the transaction level with the sequence via TLM communication with the sequencer and converting between the sequence_item on the transaction side and pin-level activity in communicating with the DUT via a virtual interface.
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UVM Monitor
Chapter - Mar 30, 2014 by Verification Methodology Team
The first task of the analysis portion of the testbench is to monitor activity on the DUT. A Monitor, like a Driver, is a constituent of an agent.
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UVM Factory
Chapter - Mar 27, 2014 by Verification Methodology Team
The purpose of the UVM factory is to enable an object of one type to be substituted with an object of a derived type without changing the testbench structure or even the testbench code.
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Post-Run Phases
Chapter - Mar 27, 2014 by Verification Methodology Team
Many analysis components perform their analysis on an ongoing basis during the simulation run.
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Backdoor Accesses
Chapter - Mar 27, 2014 by Verification Methodology Team
The UVM register model facilitates access to hardware registers in the DUT either through front door accesses or back door accesses.
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Package Organization
Chapter - Mar 27, 2014 by Verification Methodology Team
UVM organizes all of its base classes into a SystemVerilog Package.
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UVM Verification Component
Chapter - Mar 27, 2014 by Verification Methodology Team
A UVC ( U VM V erification C omponent) is a Verification Component designed for use in UVM. It is a multi-faceted definition and has different layers of meaning in different contexts.
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UVM Connect
Chapter - Mar 26, 2014 by Adam Erickson
Learn about how to use UVM Connect to link UVM and SystemC using TLM.
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UVMC Connections
Chapter - Mar 26, 2014 by Adam Erickson
To communicate, verification components must agree on the data they are exchanging and the interface used to exchange that data.
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UVMC Conversion
Chapter - Mar 26, 2014 by Adam Erickson
Object transfer requires converters to translate between the two types when crossing the SC-SV language boundary.
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UVMC Command API
Chapter - Mar 26, 2014 by Adam Erickson
The UVM Connect Command API gives SystemC users access to key UVM features in SystemVerilog.
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Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?
Paper - Mar 06, 2014 by Darron May
Getting the very best from your verification resources requires a regression system that understands the verification process and is tightly integrated with Workload Management and Distributed Resource Management software. Both requirements depend on visibility into available software and hardware resources and by combining their strengths, users can massively improve productivity by reducing unnecessary verification cycles.
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Are You Really Confident That You are Getting the Very Best From Your Verification Resources?
Resource (Paper (.PDF)) - Mar 06, 2014 by Darron May
Getting the very best from your verification resources requires a regression system that understands the verification process and is tightly integrated with Workload Management and Distributed Resource Management software.
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Bringing Regression Systems into the 21st Century
Paper - Mar 03, 2014 by Thomas Ellis
Today's verification projects are responsible for verifying some of the largest and most complex designs we have ever seen. Accordingly, the gathering and tracking of development and verification metrics, including coverage and test results, is more important than ever to project success. From figuring out what files are necessary in building a DUT (Design Under Test) and Testbench to knowing what development and verification metrics need to be gathered and tracked, the task can be significant.
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Bringing Regression Systems into the 21st Century
Resource (Paper (.PDF)) - Mar 03, 2014 by Thomas Ellis
This paper will focus on an infrastructure created at Cypress to abstract away file list and metric gathering by providing a uniform front-end shell and back-end database, boosting predictability of testbench creation and metric tracking across multiple projects. Additionally, this paper will discuss various metrics collected and the use of Verification Run Manager (VRM) toolset in gathering metrics, tracking coverage and reducing test suites to quickly and efficiently obtain coverage goals.
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Questa Verification IP, More than just a BFM
Webinar - Feb 12, 2014 by Tom Fitzpatrick
Today’s advanced UVM environments require more than a standard BFM to support environment reuse, randomized stimulus, generation of traffic scenarios, coverage collection, etc.