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Using Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
Article - Mar 31, 2014 by CJ Clark, Craig Stephan - Intellitech Corporation
IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged and tested. The standard defines register level descriptions of on-chip IP with operational descriptions via the new 1149.1 Procedural Description Language. 1, 2, 3
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Bidirectional Protocols
Chapter - Mar 31, 2014 by Verification Methodology Team
For a driver, composed of a BFM-proxy pair in the dual domain testbench, one of the most common sequence-driver use cases is where the sequencer sends request sequence_items to the driver proxy, which then executes the request phase of the pin-level protocol through the driver BFM.
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Analysis
Chapter - Mar 31, 2014 by Verification Methodology Team
Components in a UVM testbench that observe and analyze behavior of the DUT.
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Analysis Port
Chapter - Mar 31, 2014 by Verification Methodology Team
One of the unique aspects of the analysis section of a testbench is that usually there are many independent calculations and evaluations all operating on the same piece of data.
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Dealing With UVM and OVM Sequences
Article - Mar 31, 2014 by Hari Patel, Dhaval Prajapati - eInfochips
UVM/OVM methodologies are the first choice in the semiconductor industry today for creating verification environments. Because UVM/OVM are TLM-based (Transaction Level Modeling), sequence and sequence items play vital roles and must be created in the most efficient way possible in order to reduce rework and simulation time, and to make the verification environment user friendly. This article covers how to write generic and reusable sequences so that it's easy to add a new test case or sequence.
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Analysis Connections
Chapter - Mar 31, 2014 by Verification Methodology Team
An analysis component such as a Monitor sends transactions to another analysis component through a TLM connection which is a chain of objects where each calls the write(t) function in the next.
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Configuring Registers
Chapter - Mar 31, 2014 by Verification Methodology Team
During verification a programmable hardware device needs to be configured to operate in different modes. The register model can be used to automate or to semi-automate this process.
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Built-in Register Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM package contains a library of automatic test sequences which are based on the register model. These sequences can be used to do basic tests on registers and memory regions within a DUT.
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Stories of an AMS Verification Dude: Putting Stuff Together
Article - Mar 31, 2014 by Martin Vlach
I don't know how this came about, but the other day I got hired to do something called AMS Verification. It seems that there is this chip design that combines digital and analog stuff, and I was asked to make sure that all of it works when it's put together and that it does what it was meant to do when they got going in the first place.
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Metric Analyzers
Chapter - Mar 31, 2014 by Verification Methodology Team
Metric Analyzers watch and record non-functional behavior such as latency, power utilization, and other performance-related measurements.
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Objections
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM_objection class provides a means for sharing a counter between participating components and sequences.
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Separate Top-Level Modules
Chapter - Mar 31, 2014 by Verification Methodology Team
Co-emulation is done by running two distinct synchronized model evaluations - one on a hardware emulator, and one on a software simulator.
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Split Transactors
Chapter - Mar 31, 2014 by Verification Methodology Team
Driver and monitor transactors contain a mixture of transaction-level code to communicate with the testbench, and clock-driven HDL signal accessing code to communicate with the DUT through a virtual interface.
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Back Pointers
Chapter - Mar 31, 2014 by Verification Methodology Team
In the original single top bidirectional driver example, all driver activity is initiated from the testbench domain.
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Defining an API
Chapter - Mar 31, 2014 by Verification Methodology Team
As the timed portion of the traditional UVM transactor must be moved over to the HDL domain.
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Emulation-Ready Testbench Examples
Chapter - Mar 31, 2014 by Verification Methodology Team
This article steps through the process of converting a comprehensive traditional single top UVM example testbench to an equivalent one with a dual domain partitioned structure that is ready for co-emulation with Veloce.
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Sequence Priority
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM sequence use model allows multiple sequences to access a driver concurrently.
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Overriding Sequences and Sequence Items
Chapter - Mar 31, 2014 by Verification Methodology Team
Sometimes, during stimulus generation, it is useful to change the behavior of sequences or sequence items.
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Layering Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
Many protocols have a hierarchical definition - for example, PCI express, USB 3.0, and MIPI LLI all have a Transaction Layer, a Transport Layer, and a Physical Layer.
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Locking or Grabbing a Sequencer
Chapter - Mar 31, 2014 by Verification Methodology Team
There are a number of modeling scenarios where one sequence needs to have exclusive access to a driver via a sequencer.
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Hierarchical Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
When dealing with sequences, it helps to think in layers when considering the different functions that a testbench will be asked to perform.
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Portable VHDL Testbench Automation with Intelligent Testbench Automation
Article - Mar 31, 2014 by Matthew Ballance
We've come a long way since digital designs were sketched as schematics by hand on paper and tested in the lab by wiring together discrete integrated circuits, applying generated signals and checking for proper behavior. Design evolved to gate-level on a workstation and on to RTL, while verification evolved from simple directed tests to directed random, constrained-random, and systematic testing
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Register-Level Stimulus
Chapter - Mar 31, 2014 by Verification Methodology Team
Stimulus that accesses memory mapped registers should be made as abstract as possible.
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Register Model & Structure
Chapter - Mar 31, 2014 by Verification Methodology Team
In order to be able to use the UVM register model effectively, it is important to have a mental model of how it is structured in order to be able to find your way around it.
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Register Sequence Examples
Chapter - Mar 31, 2014 by Verification Methodology Team
To illustrate how the different register model access methods can be used from sequences to generate stimulus, this page contains a number of example sequences developed for stimulating the SPI master controller DUT.