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QVIP Provides Thoroughness in Verification

Article - Nov 01, 2015 Kiran Sharma, Vipin Kumar - Agnisys Technology Pvt. Ltd.

The present day designs use standard interfaces for the connection and management of functional blocks in System on Chips (SoCs). These interface protocols are so complex that, creating in-house VIPs could take a lot of engineer’s development time. A fully verified interface should include all the complex protocol compliance checking, generation and application of different test case scenarios, etc.
Minimizing Constraints to Debug Vacuous Proofs

Article - Nov 01, 2015 Anshul Jain - Oski Technology

Most false positives (i.e. missing design bugs) during the practice of model checking on industrial designs can be reduced to the problem of a failing cover. Debugging the root cause of such a failing cover can be a laborious process, when the formal testbench has many constraints. This article describes a solution to minimize the number of model checking runs to isolate a minimal set of constraints necessary for the failure. This helps improve formal verification productivity.
A Generic UVM Scoreboard

Article - Nov 01, 2015 Jacob Andersen, Kevin Seffensen, Peter Jensen - SyoSil ApS

All UVM engineers employ scoreboarding for checking DUT/reference model behavior, but only few spend their time wisely by employing an existing scoreboard architecture. The main reason is that existing frameworks have inadequately served user needs and have failed to improve user effectiveness in the debug situation. This article presents a better UVM scoreboard framework, focusing on scalability, architectural separation and connectivity to foreign environments.
Getting ISO 26262 Faults Straight

Resource (Verification Horizons Blog) - Oct 26, 2015 Avidan Efody

Random hardware faults – i.e. individual gates going nuts and driving a value they’re not supposed to – are practically expected in every electronic device, at a very low probability. When we talk about mobile or home entertainment devices, we could live with their impact. But when we talk about safety critical designs, such as automotive or medical, we could well die from it. That explains why ISO 26262 automotive safety standard is obsessed with analyzing and minimizing the risk they pose.
Getting ISO 26262 Faults Straight

Article - Oct 23, 2015 Avidan Efody

ISO 26262 for automotive requires that the impacts of random hardware faults on hardware used in vehicles are thoroughly analyzed and the risk of safety critical failures due to such faults is shown to be below a certain threshold.
New Low Power Verification Techniques

Webinar - Sep 23, 2015 Ellie Burns

This session highlights a "new school" low power methodology termed "successive refinement" that uses the strength of UPF in just such a structured approach.
Beyond UVM Registers: Better, Faster, Smarter

Paper - Sep 10, 2015 Rich Edelman

This paper proposes a re-think. A reconsideration of the goals and objectives, along with the implementation decisions. It discusses basic register model requirements and a suggested implementation and conceptual model that completely eliminates the need for a register library class, and the accompanying VPI interface to directly access the hardware.
Beyond UVM Registers: Better, Faster, Smarter

Resource (Paper (.PDF)) - Sep 10, 2015 Rich Edelman

The UVM Register package is popular, and powerful, but complex. The new model introduced in this paper is simple and fast.
New School Thinking for Fast and Efficient Verification Using EZ-VIP

Webinar - Sep 02, 2015 Jason Polychronopoulos

The session will show how to swiftly move through VIP instantiation, connection, configuration and protocol initialization, covering the use of UVM based verification IP for protocols such as PCI Express and MIPI CSI and DSI.
New School Regression Control

Webinar - Sep 01, 2015 Darron May

Getting the very best from your verification resources requires a regression system that understands the verification process and is tightly integrated with workload management and distributed resource management software. Both requirements depend on visibility into available software and hardware resources, and by combining their strengths, users can massively improve productivity by reducing unnecessary verification cycles.
Evolution of Debug

Webinar - Aug 25, 2015 Gordon Allan

In this session, Gordon Allan takes a critical look at the past, present and future challenges for debug, exploring real world situations drawn from years of experience in SoC design and verification, and describing leading-edge techniques and compelling solutions.
Conclusion: Impact of Design Size on First Silicon Success

Resource (Verification Horizons Blog) - Aug 22, 2015 Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I present verification results findings in terms of schedules, number of required spins, and classification of functional bugs. In this blog, I conclude the series on the 2014 Wilson Research Group Functional Verification Study by providing a deeper analysis of respins by design size.
Part 12: IC/ASIC Verification Results Trends

Resource (Verification Horizons Blog) - Aug 17, 2015 Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I provided data that suggest a significant amount of effort is being applied to functional verification. An important question the various studies have tried to answer is whether this increasing effort is paying off.
Part 11: IC/ASIC Power Management Trends

Resource (Verification Horizons Blog) - Aug 10, 2015 Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I presented our study findings on various verification language and library adoption trends. In this blog, I focus on power trends. Today, we see that about 73 percent of design projects actively manage power with a wide variety of techniques, ranging from simple clock-gating, to complex hypervisor/OS-controlled power management schemes.
Evolution of Debug

Resource (Slides (.PDF)) - Jul 28, 2015 Gordon Allan
Part 10: IC/ASIC Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Jul 27, 2015 Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I presented our study findings on various verification technology adoption trends. In this blog, I focus on language and library adoption trends. As previously noted, the reason some of the results sum to more than 100 percent is that some projects are using multiple languages; thus, individual projects can have multiple answers.
Part 9: IC/ASIC Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Jul 19, 2015 Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on the growing IC/ASIC design project resource trends due to rising design complexity. In this blog I examine various verification technology adoption trends.
Unleashing the Full Power of UPF Power States

Resource (Paper (.PDF)) - Jul 17, 2015
Part 8: IC/ASIC Resource Trends

Resource (Verification Horizons Blog) - Jul 13, 2015 Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on IC/ASIC design trends and rising complexity. In this blog, I plan to discuss the growing IC/ASIC design project resource trends due to rising design complexity.
Part 7: IC/ASIC Design Trends

Resource (Verification Horizons Blog) - Jul 08, 2015 Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on FPGA design and verification trends. I now will shift the focus of this series of blogs from FPGA trends to IC/ASIC trends.
EZ Verification with Questa Verification IP

Resource (Slides (.PDF)) - Jul 06, 2015 Jason Polychronopoulos
New School Connectivity Checking

Webinar - Jul 01, 2015 Mark Eslinger

This session discusses the use of a new school formal verification method which can be easily applied to solve the problem of connectivity checking with detailed case studies of how this formal app was used to automatically verify connectivity and accelerate the debug process.
Power Aware CDC Verification

Track - Jun 30, 2015 Kurt Takara

In this track, you will learn the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.
Power Aware CDC Introduction and Overview

Session - Jun 30, 2015 Kurt Takara

This session introduces the design challenges created by low power designs and the implications that these designs have on CDC verification.
Understanding Low Power Impact on CDC Logic

Session - Jun 30, 2015 Kurt Takara

This session describes the impact of low power design techniques on design and CDC logic and also explains dynamic voltage and frequency scaling (DVFS) and its effect on CDC design and verification.