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There's Productivity. And Then There's Productivity

Article - Jul 10, 2014 by Verification Horizons
UVM: What's New, What's Next and Why You Care

Webinar - Jun 25, 2014 by Tom Fitzpatrick

This session will teach you everything you need to know about the future of UVM. We'll briefly cover the new features included in UVM1.2 and how to minimize their impact, and we'll identify the key subset of UVM features that will make your environment truly reusable from block to system-level verification while providing the ideal platform for integrating new solutions and standards.
Stories of an AMS Verification Dude: Model Shmodel

Article - Jun 18, 2014 by Martin Vlach

Well, here I am again. Last time I talked about putting stuff together, and when I mean stuff, it turned out that the digital folks handed me an RTL and the analog dudes gave me a SPICE netlist. I finally got it all working together, and let ‘er rip, thinking that this was easy and I’ll be done in no time.
Use of Iterative Weight-Age Constraint to Implement Dynamic Verification Components

Article - Jun 18, 2014 by Verification Horizons
UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment

Article - Jun 18, 2014 by Verification Horizons
Best Practices for FPGA and ASIC Development

Article - Jun 16, 2014 by Josh Rensch - Siemens EDA

This is an overview of best practices for FPGA or ASIC design, assuming a traditional waterfall development process. There are four development phases: PLAN, EXECUTE, VERIFY and SUPPORT. A review step is recommended between each phase, as prescribed by DO-254. These concepts can be used in alternative methodologies, like Agile.
Optimizing Emulator Utilization

Article - Jun 16, 2014 by Russell Klein

Emulators, like Siemens EDA Veloce, are able to run designs in RTL orders of magnitude faster than logic simulators. As a result, emulation is used to execute verification runs which would be otherwise impractical in logic simulation.
UVM 1.2 Class Reference

Resource (Reference Documentation) - Jun 13, 2014 by

v1.2 The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
Stories of an AMS Verification Dude: Putting Stuff Together

Article - Jun 12, 2014 by Verification Horizons
Taming Power Aware Bugs with Questa®

Article - Jun 12, 2014 by Verification Horizons
UVM 1.2 is Coming, so be Prepared

Webinar - May 15, 2014 by Tom Fitzpatrick

In this session, you will learn everything you need to know about the future of UVM including new features, performance, backward-compatibility concerns and more.
Verification Cookbook Glossary

Chapter - Mar 31, 2014 by Verification Methodology Team

This page is an index to the glossary of various terms defined and used in the Cookbook.
Sequence Library

Chapter - Mar 31, 2014 by Verification Methodology Team

Updating your VIP/testbench sequence library is one task that you may have to perform while migrating from OVM to UVM.
Convert Phase Methods

Chapter - Mar 31, 2014 by Verification Methodology Team

Part of the OVM to UVM conversion process is to change the method names for OVM phase methods (build, connect, run, etc) to the new UVM signature for phase methods.
Migrating from OVM to UVM

Chapter - Mar 31, 2014 by Verification Methodology Team

A Roadmap for upgrading to UVM - this guide covers the minimum steps to upgrade your VIP and testbench from OVM to UVM compatibility, then goes into more detail on some further steps for UVM conformance.
Questa Compiling UVM

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM class library is an open source SystemVerilog package that relies on DPI c code in order to implement some of the library features such as regular expression matching and register backdoor accesses.
Deprecated Code

Chapter - Mar 31, 2014 by Verification Methodology Team

Accellera UVM1.0 used OVM2.1.1 as it's basis, with the intention of preserving backwards compatibility where possible.
Phase Aware

Chapter - Mar 31, 2014 by Verification Methodology Team

OVM code can be ported to run on the UVM.
Arbitrating Between Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

The uvm_sequencer has a built-in mechanism to arbitrate between sequences which could be running concurrently on a sequencer.
UVM Configuration Database

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM_config_db class is the recommended way to access the resource database.
Sequence API

Chapter - Mar 31, 2014 by Verification Methodology Team

A uvm_sequence is derived from an uvm_sequence_item and it is parameterized with the type of sequence_item that it will send to a driver via a sequencer.
Reporting Verbosity

Chapter - Mar 31, 2014 by Verification Methodology Team

UVM provides a built-in mechanism to control how many messages are printed in a UVM based testbench. This mechanism is based on comparing integer values specified when creating a debug message using either the uvm_report_info() function or the `uvm_info() macro.
Built in Debug

Chapter - Mar 31, 2014 by Verification Methodology Team

Learn about various debug techniques and support for SystemVerilog and UVM with features supplied with the UVM to assist in common problem debug.
Matlab Integration

Chapter - Mar 31, 2014 by Verification Methodology Team

MATLAB is a modeling tool often used to develop functional models of complex mathematical functions which will then be translated into RTL library blocks.
UVM Phasing

Chapter - Mar 31, 2014 by Verification Methodology Team

Phasing is a stepwise construction approach of a verification environment at runtime and the execution of required stimulus and completion of the test. UVM has an API enabling components to participate in this step by step process. The construction of structured test environments with TLM connections is done in a predetermined manner to enable smart hierarchy and connectivity management. Most verification environments use the simplest possible subset of the available phases: build, connect, run.

DAC 2025

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Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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Article - Jul 10, 2014 by Verification Horizons

Webinar - Jun 25, 2014 by Tom Fitzpatrick

Article - Jun 18, 2014 by Martin Vlach

Article - Jun 18, 2014 by Verification Horizons

Article - Jun 18, 2014 by Verification Horizons

Article - Jun 16, 2014 by Josh Rensch - Siemens EDA

Article - Jun 16, 2014 by Russell Klein

Resource (Reference Documentation) - Jun 13, 2014 by

Article - Jun 12, 2014 by Verification Horizons

Article - Jun 12, 2014 by Verification Horizons

Webinar - May 15, 2014 by Tom Fitzpatrick

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team