Search Results
Filters
Advanced Search
1776 Results
-
Join us at DVCon for a panel on Generative AI
Resource (Verification Horizons Blog) - Feb 14, 2024 by Harry Foster
Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array of exciting new capabilities. For those unfamiliar with the Verification Academy, it stands as the foremost online resource for advanced functional verification learning. We are committed to assisting you in mastering advanced functional verification skills, unlocking the numerous benefits it brings to the table.
-
Functional Verification workflow for Trusted and Assured Microelectronics
Webinar - Feb 06, 2024 by John Hallman
In this session, we will introduce apps that provide advanced automated functional checking, secure data path verification, trustworthiness assessment, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today.
-
Functional Verification workflow for Trusted and Assured Microelectronics
Resource (Slides) - Feb 06, 2024 by John Hallman
In a world of increasing trust and assurance challenges for microelectronic devices, emerging industry standards and defense policy demand early and advanced functional verification methods before ICs may be deployed in critical end products and systems. Questa technologies, built upon a foundation of world-class simulation and formal engines, provide the results desired for raising and meeting higher levels of trust and assurance for microelectronic designs.
-
Welcome to the Enhanced Verification Academy 2.0 Forums!
Resource (Verification Horizons Blog) - Jan 30, 2024 by Dave Rich
The Verification Academy is the industry’s leading resource to help you learn how to develop the skills and techniques to advance your organization’s functional verification process. It also provides forums where you can ask questions and get answers from industry peers on these verification topics. We’ve optimized the site for better viewing on a wide variety of devices, including mobile phones and tablets.
-
Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs
Resource (Slides) - Jan 24, 2024 by Luis Rodriguez
Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing.
-
Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs
Webinar - Jan 24, 2024 by Luis Rodriguez
In this session, you will learn design considerations for PCIe 5.0 and 6.0 design IP and how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs.
-
Welcome to Verification Academy 2.0!
Resource (Verification Horizons Blog) - Jan 15, 2024 by Harry Foster
Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array of exciting new capabilities. For those unfamiliar with the Verification Academy, it stands as the foremost online resource for advanced functional verification learning. We are committed to assisting you in mastering advanced functional verification skills, unlocking the numerous benefits it brings to the table.
-
UVM Framework Release 2023.4
Resource (Tarball) - Dec 31, 2023 by Bob Oden
Generator Updates: Generated qvip.compile files do not include hvl module generated by QVIP configurator when only QVIP protocols selected. BCR Updates: New step added for command line execution. Any number of these steps can be added to accommodate external commands as needed. See overlay_example.flow for details.
-
IEEE Honors Siemens Employees for Dedication to Standards Development
Resource (Verification Horizons Blog) - Dec 12, 2023 by Tom Fitzpatrick
Annually, the IEEE Standards Association (IEEE SA) recognizes outstanding participation across a variety of technical areas of standards development, leadership, and distinguished service. The IEEE SA awards ceremony was held in early December and among the awardees are two from Siemens EDA. You may recognize the names as they are two of our Verification Horizons bloggers as well.
-
UVM Connect 2.3.3 Kit
Resource (Tarball) - Dec 11, 2023 by John Stickley
The uvmc-2.3.3 release adds better support for the semantics of the TLM-2.0 base protocol and how it is used in the context of 4-phase transactions.
-
UVM Connect 2.3.3 Primer
Resource (Reference Documentation) - Dec 11, 2023 by John Stickley
The UVMC library is provided as a separate, optional package to UVM. You do not need to import the package if your environments do not require cross-language TLM connections or access to the UVM Command API.
-
UVM Connect 2.3.3 HTML
Resource (Reference Documentation) - Dec 11, 2023 by John Stickley
The UVM Connect library provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).
-
Multi-Die System Verification with Siemens’s UCIe VIP
Resource (Slides) - Dec 07, 2023 by Justin Bunnell
Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers.
-
Multi-Die System Verification with Siemens’s UCIe VIP
Webinar - Dec 07, 2023 by Justin Bunnell
In this session, we will introduce you to Siemens EDA's Verification Portfolio and then deep dive into UCIe Verification IP, discussing its key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP.
-
Hierarchical verification flow for FPGA design projects
Resource (Slides) - Nov 16, 2023 by Mamma Benmoussa Garsault - Arcys
-
Limits of verification: learnings from catastrophic system failures
Resource (Slides) - Nov 16, 2023 by Philippe Luc
-
Reducing formal verification runtime in SystemC utilizing modular interface
Resource (Slides) - Nov 16, 2023 by Hideki Kazama - Sony
-
Dusica Glisic - Veriest
Resource (Interview) - Nov 16, 2023 by Dusica Glisic - Veriest
Interview with Dusica Glisic of Veriest about the value of attending Osmosis.
-
Mihajlo Katona - Veriest
Resource (Interview) - Nov 16, 2023 by Mihajlo Katona - Veriest
Interview with Mihajlo Katona of Veriest about his presentation on combining sim and formal, formal for security, FPGA, and HLS verification, HLS and formal - and advice on starting out with formal.
-
How to sign-off cryptographic hash implementations with generated formal assertions
Resource (Slides) - Nov 16, 2023 by Tobias Ludwig - Lubis EDA
-
Reducing Formal Verification Runtime in SystemC Utilizing Modular Interface
Resource (Recording) - Nov 16, 2023 by Hideki Kazama - Sony
-
Debugging enhancements for formal property checking
Resource (Slides) - Nov 16, 2023 by Holger Busch - Infineon
-
Satinder Paul Singh - CGNT
Resource (Interview) - Nov 16, 2023 by Satinder Paul Singh - CGNT
Interview with Dusica Glisic of Veriest about the value of attending Osmosis.
-
Martin Gut - Bosch Sensortec
Resource (Interview) - Nov 16, 2023 by Martin Gut - Bosch Sensortec
Interview with Martin Gut of Bosch Sensortec about the value of learning from Osmosis different formal verification approaches.
-
How formal methods could banish the ghosts that haunt our computing systems
Resource (Recording) - Nov 16, 2023 by Prof. Wolfgang Kunz - RPTU